MMC5 pinout: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
m (oops missed these)
(I found that driving pin 92 low makes the MMC5 think it is always out of frame.)
 
(16 intermediate revisions by 4 users not shown)
Line 1: Line 1:
                                                     _____  
                                                     _____
                                                   /    \
                                                   /    \
                         Audio Amplifier Input -> / 1 100 \ -> Audio Amplifier Output
                         Audio Amplifier Input -> / 1 100 \ -> Audio Amplifier Output
                                Audio DAC (?) <- / 2    99 \ -- AGnd
                                    Audio DAC <- / 2    99 \ -- AGnd
                           Audio Pulse Waves <- / 3  (*) 98 \ ?? SL3 *
                           Audio Pulse Waves <- / 3  (*) 98 \ <> SL3
                                   +5V AVcc -- / 4        97 \ ?? CL3 *
                                   +5V AVcc -- / 4        97 \ <> CL3
                               (fr) PPU A0 -> / 5          96 \ -> CHR A2 *
                               (fr) PPU A0 -> / 5          96 \ -> CHR A2 †
                               (fr) PPU A1 -> / 6            95 \ -> CHR A1 *
                               (fr) PPU A1 -> / 6            95 \ -> CHR A1 †
                             (fr) PPU A2 -> / 7              94 \ -> CHR A0 *
                             (fr) PPU A2 -> / 7              94 \ -> CHR A0 †
                             (fr) PPU A3 -> / 8                93 \ -> (unknown output)
                             (fr) PPU A3 -> / 8                93 \ -> PRG RAM A15 (R)
                           (fr) PPU A4 -> / 9                  92 \ -> (unknown output)
                           (fr) PPU A4 -> / 9                  92 \ <- /In-Frame Detection Disable
                           (fr) PPU A5 -> / 10                  91 \ <> PPU D7 (fr)
                           (fr) PPU A5 -> / 10                  91 \ <> PPU D7 (fr)
                         (fr) PPU A6 -> / 11                    90 \ <> PPU D6 (fr)
                         (fr) PPU A6 -> / 11                    90 \ <> PPU D6 (fr)
Line 18: Line 18:
                     (r) CHR A11 <- / 16                              85 \ <> PPU D1 (fr)
                     (r) CHR A11 <- / 16                              85 \ <> PPU D1 (fr)
                   (r) CHR A12 <- / 17                                84 \ <> PPU D0 (fr)
                   (r) CHR A12 <- / 17                                84 \ <> PPU D0 (fr)
                   (r) CHR A13 <- / 18                                  83 \ -> PRG RAM +CE
                   (r) CHR A13 <- / 18                                  83 \ -> PRG RAM +CE (R)
                 (r) CHR A14 <- / 19                                    82 \ -> (unknown output)
                 (r) CHR A14 <- / 19                                    82 \ ?? (unknown input)
                 (r) CHR A15 <- / 20                                      81 \ -> (unknown output)
                 (r) CHR A15 <- / 20                                      81 \ ?? (unknown input)
               (r) CHR A16 <- / 21                                            \
               (r) CHR A16 <- / 21                                            \
               (r) CHR A17 <- / 22                                            /
               (r) CHR A17 <- / 22                                            /
Line 28: Line 28:
           (f) PPU A11 -> / 26              Nintendo MMC5              77 / <- CPU R/W (f)
           (f) PPU A11 -> / 26              Nintendo MMC5              77 / <- CPU R/W (f)
         (f) PPU A12 -> / 27      Package QFP-100, 0.65mm pitch      76 / -> PRG RAM /WE (R)
         (f) PPU A12 -> / 27      Package QFP-100, 0.65mm pitch      76 / -> PRG RAM /WE (R)
        (f) PPU A13 -> / 28                                         75 / -> (unknown output)
      (f) PPU /A13 -> / 28               (20mm × 14mm)            75 / -> PRG RAM /CE (RAM0/CE & RAM1/CE) (R)
  (unknown output) <- / 29                                          74 / -> PRG /CE (r)
  (unknown input) ?? / 29                                          74 / -> PRG /CE (r)
(unknown output) <- / 30                                          73 / -> (unknown output)
  (unknown input) ?? / 30                                          73 / -> PRG RAM A16 (R)
                     /                                            72 / -> PRG RAM 1 /CE
                     /                                            72 / -> PRG RAM 1 /CE (R)
                     \                                            71 / -> PRG RAM 0 /CE  
                     \                                            71 / -> PRG RAM 0 /CE (R)
     (f) CIRAM /CE <- \ 31                                      70 / -> PRG RAM A14
     (f) CIRAM /CE <- \ 31                                      70 / -> PRG RAM A14 (R)
     (f) CIRAM A10 <- \ 32                                    69 / -> PRG RAM A13
     (f) CIRAM A10 <- \ 32                                    69 / -> PRG RAM A13 (R)
         (f) PPU /WR -> \ 33                                  68 / <- CPU A14 (f)
         (f) PPU /WR -> \ 33                                  68 / <- CPU A14 (f)       Orientation:
         (f) PPU /RD -> \ 34                                67 / <- CPU A13 (f)
         (f) PPU /RD -> \ 34                                67 / <- CPU A13 (f)         --------------------
             (f) /IRQ <- \ 35                              66 / -> PRG A19 (r)
             (f) /IRQ <- \ 35                              66 / -> PRG A19 (r)             80        51
          (fr) CPU D0 <> \ 36                            65 / -> PRG A18 (r)
          (frR) CPU D0 <> \ 36                            65 / -> PRG A18 (r)               |        |
            (fr) CPU D1 <> \ 37                          64 / -> PRG A17 (r)
          (frR) CPU D1 <> \ 37                          64 / -> PRG A17 (r)               .-----------.
            (fr) CPU D2 <> \ 38                        63 / -> PRG A16 (r)
            (frR) CPU D2 <> \ 38                        63 / -> PRG A16 (r)             81-| Nintendo o|-50
              (fr) CPU D3 <> \ 39                      62 / -> PRG A15 (r)
            (frR) CPU D3 <> \ 39                      62 / -> PRG A15 (r)                 | MMC5      |
              (fr) CPU D4 <> \ 40                    61 / -> PRG A14 (r)
              (frR) CPU D4 <> \ 40                    61 / -> PRG A14 (r)               100-|@          |-31
                (fr) CPU D5 <> \ 41                  60 / -> PRG A13 (r)
              (frR) CPU D5 <> \ 41                  60 / -> PRG A13 (r)                   \-----------'
                (fr) CPU D6 <> \ 42                59 / <- CPU A12 (fr)
                (frR) CPU D6 <> \ 42                59 / <- CPU A12 (frR)                   |        |
                  (fr) CPU D7 <> \ 43              58 / <- CPU A11 (fr)
                (frR) CPU D7 <> \ 43              58 / <- CPU A11 (frR)                   01        30
                       +5V DVcc -- \ 44            57 / -- + Backup battery
                       +5V DVcc -- \ 44            57 / -- + Backup battery
                    (fr) CPU A0 -> \ 45          56 / -> PRG RAM Vcc
                  (frR) CPU A0 -> \ 45          56 / -> PRG RAM Vcc Output  Legend:
                    (fr) CPU A1 -> \ 46        55 / <- CPU A10 (fr)
                    (frR) CPU A1 -> \ 46        55 / <- CPU A10 (frR)         ------------------------------
                      (fr) CPU A2 -> \ 47      54 / <- CPU A9 (fr)
                    (frR) CPU A2 -> \ 47      54 / <- CPU A9 (frR)           --[MMC5]-- Power
                      (fr) CPU A3 -> \ 48  O  53 / <- CPU A8 (fr)
                      (frR) CPU A3 -> \ 48  O  53 / <- CPU A8 (frR)           ->[MMC5]<- MMC5 input
                        (fr) CPU A4 -> \ 49  52 / <- CPU A7 (fr)
                      (frR) CPU A4 -> \ 49  52 / <- CPU A7 (frR)             <-[MMC5]-> MMC5 output
                        (fr) CPU A5 -> \ 50 51 / <- CPU A6 (fr)
                        (frR) CPU A5 -> \ 50 51 / <- CPU A6 (frR)             <>[MMC5]<> Bidirectional
                                         \    /
                                         \    /                               ??[MMC5]?? Unknown
                                           \  /
                                           \  /                                   f      Famicom connection
                                           \ /  
                                           \ /                                     r      ROM chip connection
                                             V
                                             V                                     R      RAM chip connection
Orientation:


    80        51
† Default connections ("CL mode"):
    |          |
* Connect CHR-ROM A0 directly to PPU A0.
    .-----------.
* Connect CHR-ROM A1 directly to PPU A1.  
  81-| Nintendo o|-50
* Connect CHR-ROM A2 directly to PPU A2.
    | MMC5     |
* Leave output pins 94, 95 & 96 disconnected on the MMC5.
100-|@          |-31
    \-----------'
      |        |
      01        30


{| border=1
For smooth vertical scrolling in vertical split mode ("SL mode"):
! Pin || Function || Pin || Function || Pin || Function || Pin || Function
* Connect CHR-ROM A0 only to pin 94 of the MMC5.
|-
* Connect CHR-ROM A1 only to pin 95 of the MMC5.
| 1 || Amplifier Input ||rowspan=5 colspan=2| || 51 || CPU A6 ||rowspan=5 colspan=2|
* Connect CHR-ROM A2 only to pin 96 of the MMC5.
|-
| 2 || DAC? || 52 || CPU A7
|-
| 3 || Pulse Waves || 53 || CPU A8
|-
| 4 || VCC || 54 || CPU A9
|-
| 5 || PPU A0 || 55 || CPU A10
|-
| 6 || PPU A1 || 31 || CIRAM /CE || 56 || PRG RAM VCC || 81 || (unk. output)
|-
| 7 || PPU A2 || 32 || CIRAM A10 || 57 || +batt || 82 || (unk. output)
|-
| 8 || PPU A3 || 33 || PPU /WR || 58 || CPU A11 || 83 || PRG RAM +CE
|-
| 9 || PPU A4 || 34 || PPU /RD || 59 || CPU A12 || 84 || PPU D0
|-
| 10 || PPU A5 || 35 || /IRQ || 60 || PRG A13 || 85 || PPU D1
|-
| 11 || PPU A6 || 36 || CPU D0 || 61 || PRG A14 || 86 || PPU D2
|-
| 12 || PPU A7 || 37 || CPU D1 || 62 || PRG A15 || 87 || PPU D3
|-
| 13 || PPU A8 || 38 || CPU D2 || 63 || PRG A16 || 88 || PPU D4
|-
| 14 || PPU A9 || 39 || CPU D3 || 64 || PRG A17 || 89 || PPU D5
|-
| 15 || CHR A10 || 40 || CPU D4 || 65 || PRG A18 || 90 || PPU D6
|-
| 16 || CHR A11 || 41 || CPU D5 || 66 || PRG A19 || 91 || PPU D7
|-
| 17 || CHR A12 || 42 || CPU D6 || 67 || CPU A13 || 92 || (unk. output)
|-
| 18 || CHR A13 || 43 || CPU D7 || 68 || CPU A14 || 93 || (unk. output)
|-
| 19 || CHR A14 || 44 || VCC || 69 || PRG RAM A13 || 94 || CHR A0 †
|-
| 20 || CHR A15 || 45 || CPU A0 || 70 || PRG RAM A14 || 95 || CHR A1 †
|-
| 21 || CHR A16 || 46 || CPU A1 || 71 || PRG RAM 0 /CE || 96 || CHR A2 †
|-
| 22 || CHR A17 || 47 || CPU A2 || 72 || PRG RAM 1 /CE || 97 || CL3 †
|-
| 23 || CHR A18 || 48 || CPU A3 || 73 || (unk. output) || 98 || SL3 †
|-
| 24 || CHR A19 || 49 || CPU A4 || 74 || PRG /CE || 99 || GND
|-
| 25 || PPU A10 || 50 || CPU A5 || 75 || (unk. output) || 100 || Amplifier output
|-
| 26 || PPU A11 ||rowspan=5 colspan=2| || 76 || PRG RAM /WE ||rowspan=5 colspan=2|
|-
| 27 || PPU A12 || 77 || CPU R/W
|-
| 28 || PPU /A13 || 78 || /ROMSEL
|-
| 29 || (unk. output) || 79 || M2
|-
| 30 || (unk. output) || 80 || GND
|}
†PINS 94 thru 98: These set the cart to either CL or SL mode.


To set to CL mode:
"CL mode" passes the lowest PPU address bits straight to CHR ROM, while "SL mode" runs them through MMC5. SL mode allows the MMC5 to perform independent, scanline-precise vertical scrolling in vertical split mode on the side specified by register $5200. CL mode does not.
* Connect PPU A0 from the NES to A0 on the CHR ROM.
All known MMC5 cartridges use CL mode. It is not known why SL mode was not used instead; possibly ROM speed issues.
* Connect PPU A1 from the NES to A1 on the CHR ROM.  
* Connect PPU A2 from the NES to A2 on the CHR ROM.  
* Connect pins 97 and 98 together.
* Leave pins 94,95 & 96 floating on the MMC5


To set to SL mode:
* Connect pin 94 of the MMC5 to A0 of the CHR ROM.
* Connect pin 95 of the MMC5 to A1 of the CHR ROM.
* Connect pin 96 of the MMC5 to A2 of the CHR ROM.
* Connect pin 98 to ground.
* Leave pin 97 floating.
In other words, CL mode passes the lowest PPU address bits straight to CHR ROM, while SL mode runs them through MMC5. SL mode allows the MMC5 to perform smooth vertical scrolling in split mode, while CL mode does not.
Nearly all MMC5 cartridges use CL mode - it is not known why SL mode was not used instead: possibly ROM speed issues.


Audio circuit topology for HVC-ExROM boards:
Audio circuit topology for HVC-ExROM boards:

Latest revision as of 01:33, 25 March 2024

                                                   _____
                                                  /     \
                        Audio Amplifier Input -> / 1 100 \ -> Audio Amplifier Output
                                   Audio DAC <- / 2    99 \ -- AGnd
                          Audio Pulse Waves <- / 3  (*) 98 \ <> SL3
                                  +5V AVcc -- / 4        97 \ <> CL3
                              (fr) PPU A0 -> / 5          96 \ -> CHR A2 †
                             (fr) PPU A1 -> / 6            95 \ -> CHR A1 †
                            (fr) PPU A2 -> / 7              94 \ -> CHR A0 †
                           (fr) PPU A3 -> / 8                93 \ -> PRG RAM A15 (R)
                          (fr) PPU A4 -> / 9                  92 \ <- /In-Frame Detection Disable
                         (fr) PPU A5 -> / 10                   91 \ <> PPU D7 (fr)
                        (fr) PPU A6 -> / 11                     90 \ <> PPU D6 (fr)
                       (fr) PPU A7 -> / 12                       89 \ <> PPU D5 (fr)
                      (fr) PPU A8 -> / 13                         88 \ <> PPU D4 (fr)
                     (fr) PPU A9 -> / 14                           87 \ <> PPU D3 (fr)
                    (r) CHR A10 <- / 15                             86 \ <> PPU D2 (fr)
                   (r) CHR A11 <- / 16                               85 \ <> PPU D1 (fr)
                  (r) CHR A12 <- / 17                                 84 \ <> PPU D0 (fr)
                 (r) CHR A13 <- / 18                                   83 \ -> PRG RAM +CE (R)
                (r) CHR A14 <- / 19                                     82 \ ?? (unknown input)
               (r) CHR A15 <- / 20                                       81 \ ?? (unknown input)
              (r) CHR A16 <- / 21                                            \
             (r) CHR A17 <- / 22                                             /
            (r) CHR A18 <- / 23                                          80 / -- DGnd
           (r) CHR A19 <- / 24                                          79 / <- M2 (f)
          (f) PPU A10 -> / 25                                          78 / <- /ROMSEL (f)
         (f) PPU A11 -> / 26              Nintendo MMC5               77 / <- CPU R/W (f)
        (f) PPU A12 -> / 27      Package QFP-100, 0.65mm pitch       76 / -> PRG RAM /WE (R)
      (f) PPU /A13 -> / 28                (20mm × 14mm)             75 / -> PRG RAM /CE (RAM0/CE & RAM1/CE) (R)
  (unknown input) ?? / 29                                          74 / -> PRG /CE (r)
 (unknown input) ?? / 30                                          73 / -> PRG RAM A16 (R)
                   /                                             72 / -> PRG RAM 1 /CE (R)
                   \                                            71 / -> PRG RAM 0 /CE (R)
   (f) CIRAM /CE <- \ 31                                       70 / -> PRG RAM A14 (R)
    (f) CIRAM A10 <- \ 32                                     69 / -> PRG RAM A13 (R)
       (f) PPU /WR -> \ 33                                   68 / <- CPU A14 (f)        Orientation:
        (f) PPU /RD -> \ 34                                 67 / <- CPU A13 (f)         --------------------
            (f) /IRQ <- \ 35                               66 / -> PRG A19 (r)              80         51
         (frR) CPU D0 <> \ 36                             65 / -> PRG A18 (r)                |         |
          (frR) CPU D1 <> \ 37                           64 / -> PRG A17 (r)                .-----------.
           (frR) CPU D2 <> \ 38                         63 / -> PRG A16 (r)              81-| Nintendo o|-50
            (frR) CPU D3 <> \ 39                       62 / -> PRG A15 (r)                  | MMC5      |
             (frR) CPU D4 <> \ 40                     61 / -> PRG A14 (r)               100-|@          |-31
              (frR) CPU D5 <> \ 41                   60 / -> PRG A13 (r)                    \-----------'
               (frR) CPU D6 <> \ 42                 59 / <- CPU A12 (frR)                    |         |
                (frR) CPU D7 <> \ 43               58 / <- CPU A11 (frR)                   01         30
                     +5V DVcc -- \ 44             57 / -- + Backup battery
                  (frR) CPU A0 -> \ 45           56 / -> PRG RAM Vcc Output   Legend:
                   (frR) CPU A1 -> \ 46         55 / <- CPU A10 (frR)         ------------------------------
                    (frR) CPU A2 -> \ 47       54 / <- CPU A9 (frR)           --[MMC5]-- Power
                     (frR) CPU A3 -> \ 48  O  53 / <- CPU A8 (frR)            ->[MMC5]<- MMC5 input
                      (frR) CPU A4 -> \ 49   52 / <- CPU A7 (frR)             <-[MMC5]-> MMC5 output
                       (frR) CPU A5 -> \ 50 51 / <- CPU A6 (frR)              <>[MMC5]<> Bidirectional
                                        \     /                               ??[MMC5]?? Unknown
                                         \   /                                    f      Famicom connection
                                          \ /                                     r      ROM chip connection
                                           V                                      R      RAM chip connection

† Default connections ("CL mode"):

  • Connect CHR-ROM A0 directly to PPU A0.
  • Connect CHR-ROM A1 directly to PPU A1.
  • Connect CHR-ROM A2 directly to PPU A2.
  • Leave output pins 94, 95 & 96 disconnected on the MMC5.

For smooth vertical scrolling in vertical split mode ("SL mode"):

  • Connect CHR-ROM A0 only to pin 94 of the MMC5.
  • Connect CHR-ROM A1 only to pin 95 of the MMC5.
  • Connect CHR-ROM A2 only to pin 96 of the MMC5.

"CL mode" passes the lowest PPU address bits straight to CHR ROM, while "SL mode" runs them through MMC5. SL mode allows the MMC5 to perform independent, scanline-precise vertical scrolling in vertical split mode on the side specified by register $5200. CL mode does not. All known MMC5 cartridges use CL mode. It is not known why SL mode was not used instead; possibly ROM speed issues.


Audio circuit topology for HVC-ExROM boards:

MMC5 audio.png

Retrieved from "https://www.nesdev.org/w/index.php?title=MMC5_pinout&oldid=21686"