VRC3: Difference between revisions

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[[Category:ASIC mappers]][[Category:in NesCartDB]]
{{Infobox_iNES_mapper
The Konami VRC3 is an [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]] apparently used only for the game ''Salamander''. The [[iNES]] format assigns [[iNES Mapper 073|mapper 73]] to VRC3.
|name=VRC3
|company=Konami
|mapper=73
|nescartdbgames=1
|complexity=ASIC
|boards=350685
|pinout=VRC3 pinout
|prgmax=128K
|prgpage=16K
|wrammax=8K
|wrampage=8K, fixed
|chrmax=8K RAM
|chrpage=8K, fixed
|mirroring=Fixed H or V, controlled by solder pads
|busconflicts=No
|irq=Yes
}}
[[Category:ASIC mappers]][[Category:in NesCartDB]][[Category:Mappers with cycle IRQs]]
The Konami VRC3 is an [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]] apparently used only for the game [https://nescartdb.com/profile/view/1783/salamander Salamander]. The [[iNES]] format assigns '''mapper 73''' to VRC3.




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== Overview ==
== Banks ==
* PRG ROM size: Up to 128 KB
* CPU $6000-$7FFF: optional 8 KiB PRG RAM bank
* PRG ROM bank size: 16 KB at $8000
* CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
* PRG RAM: 8 KB at $6000
* CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last bank
* CHR: 8 KB RAM, not swappable
* Nametable [[mirroring]]: Solder pads select vertical or horizontal mirroring
* Subject to [[bus conflict]]s: No
 
See [[VRC3 pinout]] for chip pinout.


== Registers ==
== Registers ==
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       +--- IRQ Mode (1=8-bit counter, 0=16-bit counter)
       +--- IRQ Mode (1=8-bit counter, 0=16-bit counter)


Any write to this register will acknowledge the pending IRQ.  If this register is written to with the 'E' bit set, the 16-bit IRQ counter is reloaded with the 16-bit Latch value (set by writes to $8000-$BFFF).
Any write to this register will acknowledge the pending IRQ.  If this register is written to with the '''E''' bit set, the 16-bit IRQ counter is reloaded with the 16-bit Latch value (set by writes to $8000-$BFFF).




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  .... ....
  .... ....


Any write to this register will acknowledge the pending IRQ.  In addition, the 'A' control bit moves to the 'E' control bit, enabling or disabling IRQs. Writes to this register do not affect the current state of the IRQ counter.
Any write to this register will acknowledge the pending IRQ.  In addition, the '''A''' control bit moves to the '''E''' control bit, enabling or disabling IRQs. Writes to this register do not affect the current state of the IRQ counter.




== IRQ Counter Operation ==
== IRQ Counter Operation ==


IRQs on this mapper are generated through a 16-bit counter, which is incremented each CPU cycle (if enabled). When it overflows from $FFFF, an IRQ is generated, and the counter is reloaded with the 16-bit latch value.
VRC3 IRQs operate differently from other VRCs.  The counter is 16 bits instead of 8 bits, and there is no
scanline mode, only CPU cycle mode. Other aspects, however, are very similar.
 
IRQs on this mapper are generated through a 16-bit counter, which is incremented each CPU cycle (if enabled). When it overflows from $FFFF, an IRQ is generated, and the counter is reloaded with the 16-bit latch value.
 
When the IRQ mode bit ('''M''') is set, the upper 8 bits of the counter are ignored (and never incremented) and IRQs are generated when the lower 8 bits overflow from $FF. When the IRQ is triggered, only the low 8 bits are reloaded from the latch value. Reloading with a write to $C000 with '''E''' set will always reload all 16 bits, regardless of mode.


When the IRQ mode bit ('M') is set, the upper 8 bits of the counter are ignored and IRQs are generated when the lower 8 bits overflow from $FF.
When IRQs are disabled ('''E''' control bit clear), the IRQ counter does not increment.


When IRQs are disabled ('E' control bit clear), the IRQ counter does not increment.
Writing to the acknowledge register at $D000 automatically moves control bit '''A''' into control bit '''E''', allowing the IRQ to be easily re-enabled while acknowledging.


== Disch's Notes ==
==References==
  Here are Disch's original notes: 
* [http://www.romhacking.net/documents/362/ Disch's Mapper Notes]
  ========================
  =  Mapper 073          =
  ========================
 
  aka
  --------------------------
  VRC3
 
 
  Example Games:
  --------------------------
  Salamander
 
 
  Registers:
  --------------------------
 
  Range,Mask:  $8000-FFFF, $F000
 
    $8000:  [.... IIII]   Bits  0- 3 of IRQ reload value
    $9000:  [.... IIII]  Bits  4- 7 of IRQ reload value
    $A000:  [.... IIII]  Bits  8-11 of IRQ reload value
    $B000:  [.... IIII]  Bits 12-15 of IRQ reload value
 
    $C000:  [.... .MEA]  IRQ Control
      M = IRQ Mode (0=16-bit mode, 1=8-bit mode)
      E = IRQ Enable (0=disabled, 1=enabled)
      A = Enable-on-Acknowledge (see IRQ section)
 
    $D000:  [.... ....]  IRQ Acknowledge (see IRQ section)
 
    $F000:  [.... PPPP]  PRG Select (16k @ $8000)
 
 
  PRG Setup:
  ---------------------------
 
        $8000  $A000  $C000  $E000 
      +---------------+---------------+
      |    $F000    |    { -1}    |
      +---------------+---------------+
 
 
  IRQs:
  ---------------------------
 
  VRC3 IRQs operate differently from other VRCs.  The counter is 16 bits instead of 8 bits, and there is no
  scanline mode -- only CPU cycle mode.  Other aspects, however, are very similar.
 
  $8000-B000 set the 16-bit reload value (not the actual IRQ counter).  When $C000 is written to with the 'E'
  bit set, the reload value is copied into the actual IRQ counter.
 
  When enabled, the IRQ counter will increment by 1 every CPU cycle until it wraps, at which point the IRQ
  counter is reloaded with the reload value (relevent bits only!  see Modes below) and an IRQ is tripped.
 
  Any write to $C000 or $D000 will acknowledge the IRQ.
 
  Any write to $D000 will also copy the 'A' control bit to the 'E' control bit... enabling or disabling IRQs.
  This does not change the contents of the IRQ counter.
 
 
  Modes:
  ---------------------------
  There are 8-bit and 16-bit modes for the IRQ counter, as controlled by the 'M' bit in $C000.
 
    In 16-bit mode (M=0):
      - Counter is a full 16-bits.
      - IRQ is triggered when IRQ counter is incremented from $FFFF
 
 
    In 8-bit mode (M=1):
      - Only the low 8-bit bits of counter are used
      - IRQ is triggered when low 8 bits of IRQ counter are incremented from $FF
      - Incrementing the low bits *never* alters the high bits of the counter
      - When low 8 bits wrap, only the low 8 bits are copied from the reload value... high bits remain unchanged
      - Reloading via $C000 write will still reload all 16 bits.

Latest revision as of 01:56, 14 September 2023

VRC3
Company Konami
Games 1 in NesCartDB
Complexity ASIC
Boards 350685
Pinout VRC3 pinout
PRG ROM capacity 128K
PRG ROM window 16K
PRG RAM capacity 8K
PRG RAM window 8K, fixed
CHR capacity 8K RAM
CHR window 8K, fixed
Nametable mirroring Fixed H or V, controlled by solder pads
Bus conflicts No
IRQ Yes
Audio No
iNES mappers 073

The Konami VRC3 is an ASIC mapper apparently used only for the game Salamander. The iNES format assigns mapper 73 to VRC3.



Banks

  • CPU $6000-$7FFF: optional 8 KiB PRG RAM bank
  • CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
  • CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last bank

Registers

PRG Select ($F000-$FFFF)

7  bit  0
---------
.... .PPP
      |||
      +++- Select 16 KB PRG ROM at $8000


IRQ Latch 0 ($8000-$8FFF)

7  bit  0
---------
.... LLLL
     ||||
     ++++- Bits 0-3 of IRQ latch.

IRQ Latch 1 ($9000-$9FFF)

7  bit  0
---------
.... LLLL
     ||||
     ++++- Bits 4-7 of IRQ latch.

IRQ Latch 2 ($A000-$AFFF)

7  bit  0
---------
.... LLLL
     ||||
     ++++- Bits 8-11 of IRQ latch.

IRQ Latch 3 ($B000-$BFFF)

7  bit  0
---------
.... LLLL
     ||||
     ++++- Bits 12-15 of IRQ latch.


IRQ Control ($C000-$CFFF)

7  bit  0
---------
.... .MEA
      |||
      ||+- IRQ Enable on Acknowledgement (see $D000)
      |+-- IRQ Enable (1=enabled)
      +--- IRQ Mode (1=8-bit counter, 0=16-bit counter)

Any write to this register will acknowledge the pending IRQ. If this register is written to with the E bit set, the 16-bit IRQ counter is reloaded with the 16-bit Latch value (set by writes to $8000-$BFFF).


IRQ Acknowledge ($D000-$DFFF)

7  bit  0
---------
.... ....

Any write to this register will acknowledge the pending IRQ. In addition, the A control bit moves to the E control bit, enabling or disabling IRQs. Writes to this register do not affect the current state of the IRQ counter.


IRQ Counter Operation

VRC3 IRQs operate differently from other VRCs. The counter is 16 bits instead of 8 bits, and there is no scanline mode, only CPU cycle mode. Other aspects, however, are very similar.

IRQs on this mapper are generated through a 16-bit counter, which is incremented each CPU cycle (if enabled). When it overflows from $FFFF, an IRQ is generated, and the counter is reloaded with the 16-bit latch value.

When the IRQ mode bit (M) is set, the upper 8 bits of the counter are ignored (and never incremented) and IRQs are generated when the lower 8 bits overflow from $FF. When the IRQ is triggered, only the low 8 bits are reloaded from the latch value. Reloading with a write to $C000 with E set will always reload all 16 bits, regardless of mode.

When IRQs are disabled (E control bit clear), the IRQ counter does not increment.

Writing to the acknowledge register at $D000 automatically moves control bit A into control bit E, allowing the IRQ to be easily re-enabled while acknowledging.

References

Retrieved from "https://www.nesdev.org/w/index.php?title=VRC3&oldid=21300"