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| | #REDIRECT [[NES-EVENT]] |
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| [[Category:iNES Mappers|105]][[Category:Multicart mappers|105]][[Category:in NesCartDB|105]] | | [[Category:iNES Mappers|105]][[Category:Multicart mappers|105]][[Category:in NesCartDB|105]] |
| Here are Disch's original notes:
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| ========================
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| = Mapper 105 =
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| ========================
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|
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| aka
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| --------------------------
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| [[NES-EVENT]]
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|
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|
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| Example Game:
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| --------------------------
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| Nintendo World Championships 1990
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|
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|
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| Notes:
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| ---------------------------
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| This mapper is an [[MMC1]] with crazy wiring and a huge 30-bit CPU cycle driven IRQ counter. Registers are all
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| internal and not directly accessable -- and the latch must be written to 1 bit at a time -- just like on a
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| normal MMC1. For details on how regs are written to, see [[INES Mapper 001|mapper 001]].
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|
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| This mapper has 8k CHR-RAM, and it is not swappable.
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|
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|
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| Registers:
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| ---------------------------
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|
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| Note that like a normal MMC1, registers are internal and not accessed directly.
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|
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|
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| $8000-9FFF: [.... PSMM] Same as MMC1 (but CHR mode bit isn't used)
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|
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| $A000-BFFF: [...I OAA.]
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| I = IRQ control / initialization toggle
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| O = PRG Mode/Chip select
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| A = PRG Reg 'A'
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|
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| $C000-DFFF: [.... ....] Unused
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|
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| $E000-FFFF: [...W BBBB]
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| W = WRAM disable (same as MMC1)
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| B = PRG Reg 'B'
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|
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|
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|
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| Powerup / Reset / Initialization:
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| ---------------------------
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|
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| On powerup and reset, the first 32k of PRG (from the first PRG chip) is selected at $8000 *no matter what*.
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| PRG cannot be swapped until the mapper has been "initialized" by setting the 'I' bit to 0, then to '1'. This
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| toggling will "unlock" PRG swapping on the mapper.
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|
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| Note 'I' also controls the IRQ counter (see below)
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|
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|
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| PRG Setup:
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| ---------------------------
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|
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| There are 2 PRG chips, each 128k. The 'O' bit selects between the chips, and also determines which PRG Reg
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| is used to select the page.
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|
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| O=0: Use first PRG chip (first 128k), use 'A' PRG Reg, 32k swap
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| O=1: Use second PRG chip (second 128k), use 'B' PRG Reg, MMC1 style swap
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|
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| In addition, if the mapper has not been "unlocked", the first 32k of the first chip is always selected
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| regardless (as if $A000 contained $00).
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|
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| Modes as listed below:
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|
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| $8000 $A000 $C000 $E000
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| +-------------------------------+
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| Uninitialized: | { 0 } | <-- use first 128k
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| +-------------------------------+
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| O=0: | $A000 | <-- use first 128k
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| +-------------------------------+
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| O=1, P=0: | <$E000> | <-- use second 128k
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| +-------------------------------+
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| O=1, P=1, S=0: | { 0 } | $E000 | <-- use second 128k
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| +---------------+---------------+
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| O=1, P=1, S=1: | $E000 | {$07} | <-- use second 128k
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| +---------------+---------------+
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|
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|
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| IRQ Counter:
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| ---------------------------
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|
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| The 'I' bit in $A000 controls the IRQ counter. When cleared, the IRQ counter counts up every cycle. When
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| set, the IRQ counter is reset to 0 and stays there (does not count), and the pending IRQ is acknowledged.
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|
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| The cart has 4 dipswitches which control how high the counter must reach for an IRQ to be generated.
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| The IRQ counter is 30 bits wide.. when it reaches the following value, an IRQ is fired:
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| [1D CBAx xxxx xxxx xxxx xxxx xxxx xxxx]
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| ^ ^^^
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| either 0 or 1, depending on the corresponding dipswitch.
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|
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| So if all dipswitches are open (use '0' above), the counter must reach $20000000.
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| If all dipswitches are closed (use '1' above), the counter must reach $3E000000.
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| etc
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|
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| In the official tournament, 'C' was closed, and the others were open, so the counter had to reach $2800000.
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| Note that:
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| *PPU A12 is still connected to the MMC1 (so the register at $C000 exists, and the bit in $8000 to control CHR banking mode still exists, and writing a value with that bit set would make the register at $C000 relevant), and
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| *MMC1 PRG A14 is connected to both PRG ROMs (so writes to $8000 could select either 16+16 banking mode, and then writes to $E000 could cause either the first or second 16K of the first ROM to be mapped at both $8000 and $C000 before the timer was unlocked)
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