Mapper 208 pinout: Difference between revisions
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Krzysiobal (talk | contribs) (Created page with "Category: pinouts +---v---+ CPU A14 -> | 1 28| -- VCC CPU A13 -> | 2 27| <- M2 CPU A12 -> | 3 26| <- CPU /ROMSEL CPU A11 -> | 4 25| <- CPU R/!W CPU A1 -> | 5 24| <- CPU D0 CPU A0 -> | 6 23| <- CPU D1 PPU A10 -> | 7 22| <- CPU D2 PPU A11 -> | 8 21| -- GND OR A -> | 9 20| <- CPU D3 OR B -> |10 19| <- CPU D4 PRG A16 <- |11 18| <- CPU D5 PRG A15 <- |12 17| <- CPU D6 OR Y <- |13 16| <- CPU D7 GND -- |14...") |
m (link back to mapper description) |
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| Line 1: | Line 1: | ||
[[Category: pinouts]] | [[Category: pinouts]][[iNES Mapper 208]] | ||
+---v---+ | +---v---+ | ||
CPU A14 -> | 1 28| -- VCC | CPU A14 -> | 1 28| -- VCC | ||
Latest revision as of 17:13, 15 August 2022
+---v---+
CPU A14 -> | 1 28| -- VCC
CPU A13 -> | 2 27| <- M2
CPU A12 -> | 3 26| <- CPU /ROMSEL
CPU A11 -> | 4 25| <- CPU R/!W
CPU A1 -> | 5 24| <- CPU D0
CPU A0 -> | 6 23| <- CPU D1
PPU A10 -> | 7 22| <- CPU D2
PPU A11 -> | 8 21| -- GND
OR A -> | 9 20| <- CPU D3
OR B -> |10 19| <- CPU D4
PRG A16 <- |11 18| <- CPU D5
PRG A15 <- |12 17| <- CPU D6
OR Y <- |13 16| <- CPU D7
GND -- |14 15| -> CIR A10
'-------'
UNNAMED
0.6" 40-pin PDIP
Source: [[1]]
