VRC2 pinout: Difference between revisions

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Konami [[VRC2]] and [[VRC4]]: 0.6" 40-pin PDIP (iNES Mappers [[iNES Mapper 021|21]], [[iNES Mapper 022|22]], [[iNES Mapper 023|23]], and [[iNES Mapper 025|25]])
Konami [[VRC2 and VRC4]]: 0.6" 40-pin PDIP (iNES Mappers '''21''', '''22''', '''23''', and '''25''')
   r: connects to ROM
   r: connects to ROM
   f: connects to Famicom
   f: connects to Famicom
 
                  .--\/--.  
                      .--\/--.
    (f) CPU A13 -> |01  40| -- +5V
      (f) CPU A13 -> |01  40| -- +5V
    (f) CPU A14 -> |02  39| -> PRG A17 (r)
      (f) CPU A14 -> |02  39| -> PRG A17 (r)
    (fr) CPU Ax -> |03  38| -> PRG A15 (r)
      (fr) CPU Ax -> |03  38| -> PRG A15 (r)
    (fr) CPU Ay -> |04  37| <- CPU A12 (f)
      (fr) CPU Ay -> |04  37| <- CPU A12 (f)
    (f) PPU A12 -> |05  36| -> PRG A14 (r)
      (f) PPU A12 -> |05  36| -> PRG A14 (r)
    (f) PPU A11 -> |06  35| -> PRG A13 (r)
      (f) PPU A11 -> |06  35| -> PRG A13 (r)
    (f) PPU A10 -> |07  34| -> PRG A16 (r)
      (f) PPU A10 -> |07  34| -> PRG A16 (r)
    (r) PRG /CE <- |08  33| <- CPU D0 (fr)
      (r) PRG /CE <- |08  33| <- CPU D0 (fr)
    (f) CPU R/W -> |09  32| <- CPU D1 (fr)
      (f) CPU R/W -> |09  32| <- CPU D1 (fr)
     (r) CHR /CE <- |10  31| <- CPU D2 (fr)
     (CHR /CE) OR Y <- |10  31| <- CPU D2 (fr)
     (f) PPU A13 -> |11  30| <- CPU D4 (fr)
     (PPU A13) OR B -> |11  30| <- CPU D4 (fr)
     (f) PPU /OE -> |12  29| <- CPU D3 (fr)
     (PPU /RD) OR A -> |12  29| <- CPU D3 (fr)
    (f) PPU A10 -> |13  28| -> CHR A17 (r)
    (f) CIRAM A10 <- |13  28| -> CHR A17 (r)
    (f) /ROMSEL -> |14  27| -> CHR A15 (r)
      (f) /ROMSEL -> |14  27| -> CHR A15 (r)
        (f) M2 -> |15  26| -> CHR A12 (r)
            (f) M2 -> |15  26| -> CHR A12 (r)
              ? <- |16  25| -> CHR A14 (r)
  VRC4 (f) CHR A18 <- |16  25| -> CHR A14 (r)
  VRC4 (f) /IRQ <- |17  24| -> CHR A13 (r)
    VRC4 (f) /IRQ <- |17  24| -> CHR A13 (r)
              ? -- |18  23| -> CHR A11 (r)
      VRC4 /WR9003 <- |18  23| -> CHR A11 (r)
  VRC4 WRAM /CE <- |19  22| -> CHR A16 (r)
    VRC4 WRAM /CE <- |19  22| -> CHR A16 (r)
            GND -- |20  21| -> CHR A10 (r)
              GND -- |20  21| -> CHR A10 (r)
                  `------'
                      `------'
   3, 4: see below
   3, 4: see below
  16: on VRC4, connectable (but not by default) to CHR A18. No known way to control.
The VRC2's pins 16-19 seem to have been [http://forums.nesdev.org/viewtopic.php?t=8569 intended for a never-seen-used EEPROM]
The VRC2's pins 16-19 seem to have been [http://forums.nesdev.org/viewtopic.php?t=8569 intended for a never-seen-used EEPROM]


Konami was greatly fond of making minor variations from one game to the next, presumably to make life harder on pirates.
Konami was greatly fond of making minor variations from one game to the next, presumably to make life harder on pirates.


VRC4a, PCB 352398, mapper 21 submapper 9
VRC4a, PCB 352398, mapper 21
     '''(fr) CPU A2''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A2''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
     '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
VRC2c, PCB 351948, mapper 25 submapper 15 &<br/>
VRC4b, PCB 351406, mapper 25
VRC4b, PCB 351406, mapper 25 submapper 1
     '''(fr) CPU A0''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A0''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
     '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
VRC4c, PCB 352889, mapper 21 submapper 14
VRC2c, PCB 351948, mapper 25
    '''(fr) CPU A0''' -> |03  38| -> PRG A15 (r)
    '''(fr) CPU A1''' -> |04  37| <- '''74'139 /Y2'''[https://forums.nesdev.org/viewtopic.php?t=6584]
* The additional logic evaluates (/ROMSEL OR CPUA12), preventing bus conflicts between the Microwire interface and the PRG RAM on the board by making I/O to $6000-$6FFF instead appear to the VRC2 to be happening to $7000-$7FFF
VRC4c, PCB 352889, mapper 21
     '''(fr) CPU A7''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A7''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A6''' -> |04  37| <- CPU A12 (f)
     '''(fr) CPU A6''' -> |04  37| <- CPU A12 (f)
VRC4d, PCB 352400, mapper 25 submapper 3
VRC4d, PCB 352400, mapper 25
     '''(fr) CPU A2''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A2''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A3''' -> |04  37| <- CPU A12 (f)
     '''(fr) CPU A3''' -> |04  37| <- CPU A12 (f)
VRC4e, PCB 352396, mapper 23 submapper 10
VRC4e, PCB 352396, mapper 23
     '''(fr) CPU A3''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A3''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A2''' -> |04  37| <- CPU A12 (f)
     '''(fr) CPU A2''' -> |04  37| <- CPU A12 (f)
VRC2b, PCBs 350603, 350636, 350926, and 351179, mapper 23 submapper 15
VRC2b, PCBs 350603, 350636, 350926, and 351179, mapper 23
     '''(fr) CPU A1''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A1''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A0''' -> |04  37| <- CPU A12 (f)
     '''(fr) CPU A0''' -> |04  37| <- CPU A12 (f)
Line 53: Line 55:
     '''(fr) CPU A0''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A0''' -> |03  38| -> PRG A15 (r)
     '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
     '''(fr) CPU A1''' -> |04  37| <- CPU A12 (f)
                   ⋮    ⋮
                   :      :
    (f) PPU A10 -> |13  28| -> '''CHR A16 (r)'''
  (f) CIRAM A10 <- |13  28| -> '''CHR A16 (r)'''
     (f) /ROMSEL -> |14  27| -> '''CHR A14 (r)'''
     (f) /ROMSEL -> |14  27| -> '''CHR A14 (r)'''
         (f) M2 -> |15  26| -> '''CHR A11 (r)'''
         (f) M2 -> |15  26| -> '''CHR A11 (r)'''
              ? -- |16  25| -> '''CHR A13 (r)'''
  VRC2 µWire DO -> |16  25| -> '''CHR A13 (r)'''
   VRC4 (f) /IRQ <- |17  24| -> '''CHR A12 (r)'''
   VRC2 µWire DI <- |17  24| -> '''CHR A12 (r)'''
              ? -- |18  23| -> '''CHR A10 (r)'''
  VRC2 µWire SK <- |18  23| -> '''CHR A10 (r)'''
   VRC4 WRAM /CE <- |19  22| -> '''CHR A15 (r)'''
   VRC2 µWire CS <- |19  22| -> '''CHR A15 (r)'''
             GND -- |20  21| -> '''n/c'''
             GND -- |20  21| -> '''n/c'''
The VRC2 µWire interface is thought to be nonfunctional.


Sources:
* https://web.archive.org/web/20140920211213/http://nintendoallstars.w.interia.pl/romlab/vrcp.htm
* http://forums.nesdev.org/viewtopic.php?t=8569
[[Category:Pinouts]]
[[Category:Pinouts]]
==Pirate clones==
There exist [http://forums.nesdev.org/viewtopic.php?f=9&t=8569&start=15#p240820 pirate versions] of both VRC2 and VRC4. The pinout and operation is the same:
*VRC2: 23C3662, AX-40G, 23C269, AX5705, nameless
*VRC4: AX5208P, AX5208C, V4, PT8155
Note:
* PT8155 seems to have CHR-A17 and PRG-A17 (and maybe PRG-A18?) pins either broken, repurposed or not connected at all, because there exists at least one PCB with that chip (P-4073 PP-43KII, game ''Wai Wai World 2'') that has additional logic to provide missing CHR-A17 and PRG-A17 lines (see [[:File:PT8155_Wai_Wai_World_2.png|schematic]])

Latest revision as of 01:32, 17 November 2021

Konami VRC2 and VRC4: 0.6" 40-pin PDIP (iNES Mappers 21, 22, 23, and 25) 

 r: connects to ROM
 f: connects to Famicom

                     .--\/--.
      (f) CPU A13 -> |01  40| -- +5V
      (f) CPU A14 -> |02  39| -> PRG A17 (r)
      (fr) CPU Ax -> |03  38| -> PRG A15 (r)
      (fr) CPU Ay -> |04  37| <- CPU A12 (f)
      (f) PPU A12 -> |05  36| -> PRG A14 (r)
      (f) PPU A11 -> |06  35| -> PRG A13 (r)
      (f) PPU A10 -> |07  34| -> PRG A16 (r)
      (r) PRG /CE <- |08  33| <- CPU D0 (fr)
      (f) CPU R/W -> |09  32| <- CPU D1 (fr)
   (CHR /CE) OR Y <- |10  31| <- CPU D2 (fr)
   (PPU A13) OR B -> |11  30| <- CPU D4 (fr)
   (PPU /RD) OR A -> |12  29| <- CPU D3 (fr)
    (f) CIRAM A10 <- |13  28| -> CHR A17 (r)
      (f) /ROMSEL -> |14  27| -> CHR A15 (r)
           (f) M2 -> |15  26| -> CHR A12 (r)
 VRC4 (f) CHR A18 <- |16  25| -> CHR A14 (r)
    VRC4 (f) /IRQ <- |17  24| -> CHR A13 (r)
     VRC4 /WR9003 <- |18  23| -> CHR A11 (r)
    VRC4 WRAM /CE <- |19  22| -> CHR A16 (r)
              GND -- |20  21| -> CHR A10 (r)
                     `------'
 3, 4: see below

The VRC2's pins 16-19 seem to have been intended for a never-seen-used EEPROM

Konami was greatly fond of making minor variations from one game to the next, presumably to make life harder on pirates.

VRC4a, PCB 352398, mapper 21 

   (fr) CPU A2 -> |03  38| -> PRG A15 (r)
   (fr) CPU A1 -> |04  37| <- CPU A12 (f)

VRC4b, PCB 351406, mapper 25 

   (fr) CPU A0 -> |03  38| -> PRG A15 (r)
   (fr) CPU A1 -> |04  37| <- CPU A12 (f)

VRC2c, PCB 351948, mapper 25 

   (fr) CPU A0 -> |03  38| -> PRG A15 (r)
   (fr) CPU A1 -> |04  37| <- 74'139 /Y2[1]
  • The additional logic evaluates (/ROMSEL OR CPUA12), preventing bus conflicts between the Microwire interface and the PRG RAM on the board by making I/O to $6000-$6FFF instead appear to the VRC2 to be happening to $7000-$7FFF

VRC4c, PCB 352889, mapper 21 

   (fr) CPU A7 -> |03  38| -> PRG A15 (r)
   (fr) CPU A6 -> |04  37| <- CPU A12 (f)

VRC4d, PCB 352400, mapper 25 

   (fr) CPU A2 -> |03  38| -> PRG A15 (r)
   (fr) CPU A3 -> |04  37| <- CPU A12 (f)

VRC4e, PCB 352396, mapper 23 

   (fr) CPU A3 -> |03  38| -> PRG A15 (r)
   (fr) CPU A2 -> |04  37| <- CPU A12 (f)

VRC2b, PCBs 350603, 350636, 350926, and 351179, mapper 23 

   (fr) CPU A1 -> |03  38| -> PRG A15 (r)
   (fr) CPU A0 -> |04  37| <- CPU A12 (f)

VRC2a, PCB 351618, mapper 22 (no submapper necessary) 

   (fr) CPU A0 -> |03  38| -> PRG A15 (r)
   (fr) CPU A1 -> |04  37| <- CPU A12 (f)
                  :      :
 (f) CIRAM A10 <- |13  28| -> CHR A16 (r)
   (f) /ROMSEL -> |14  27| -> CHR A14 (r)
        (f) M2 -> |15  26| -> CHR A11 (r)
 VRC2 µWire DO -> |16  25| -> CHR A13 (r)
 VRC2 µWire DI <- |17  24| -> CHR A12 (r)
 VRC2 µWire SK <- |18  23| -> CHR A10 (r)
 VRC2 µWire CS <- |19  22| -> CHR A15 (r)
           GND -- |20  21| -> n/c

The VRC2 µWire interface is thought to be nonfunctional.

Sources:


Pirate clones

There exist pirate versions of both VRC2 and VRC4. The pinout and operation is the same:

  • VRC2: 23C3662, AX-40G, 23C269, AX5705, nameless
  • VRC4: AX5208P, AX5208C, V4, PT8155

Note:

  • PT8155 seems to have CHR-A17 and PRG-A17 (and maybe PRG-A18?) pins either broken, repurposed or not connected at all, because there exists at least one PCB with that chip (P-4073 PP-43KII, game Wai Wai World 2) that has additional logic to provide missing CHR-A17 and PRG-A17 lines (see schematic)
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