Talk:VRC6: Difference between revisions
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== Extended VRC6 PPU banking modes == | |||
The VRC6 documentation (currently linked from [http://forums.nesdev.org/viewtopic.php?f=2&t=10611 here]) seems to indicate that register $B003 has quite a lot more bits than we currently know about: | The VRC6 documentation (currently linked from [http://forums.nesdev.org/viewtopic.php?f=2&t=10611 here]) seems to indicate that register $B003 has quite a lot more bits than we currently know about: | ||
* D0/D1: CHR/NT Bank mode | * D0/D1: CHR/NT Bank mode | ||
| Line 12: | Line 13: | ||
: That's funny- I noticed something related when I was reformatting up the [[VRC6 pinout]] page, pin 32.—[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 13:54, 23 October 2013 (MDT) | : That's funny- I noticed something related when I was reformatting up the [[VRC6 pinout]] page, pin 32.—[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 13:54, 23 October 2013 (MDT) | ||
== Raw data == | |||
Here's the raw data I received from BootGod that I used to determine the exact banking pattern of the VRC6: | |||
b003 0000 0400 0800 0c00 1000 1400 1800 1c00 2000 2400 2800 2c00 | |||
00 81 88 90 99 A0 A9 B1 B8 71 71 78 78 | |||
01 81 81 88 88 90 90 99 99 60 69 71 78 | |||
02 81 88 90 99 A0 A0 A9 A9 71 78 71 78 | |||
03 81 88 90 99 A0 A0 A9 A9 71 78 71 78 | |||
04 81 88 90 99 A0 A9 B1 B8 71 78 71 78 | |||
05 81 81 88 88 90 90 99 99 60 69 71 78 | |||
06 81 88 90 99 A0 A0 A9 A9 71 71 78 78 | |||
07 81 88 90 99 A0 A0 A9 A9 71 71 78 78 | |||
08 81 88 90 99 A0 A9 B1 B8 71 71 78 78 | |||
09 81 81 88 88 90 90 99 99 60 69 71 78 | |||
0A 81 88 90 99 A0 A0 A9 A9 71 78 71 78 | |||
0B 81 88 90 99 A0 A0 A9 A9 71 78 71 78 | |||
0C 81 88 90 99 A0 A9 B1 B8 71 78 71 78 | |||
0D 81 81 88 88 90 90 99 99 60 69 71 78 | |||
0E 81 88 90 99 A0 A0 A9 A9 71 71 78 78 | |||
0F 81 88 90 99 A0 A0 A9 A9 71 71 78 78 | |||
10 81 88 90 99 A0 A9 B1 B8 B1 B1 B8 B8 | |||
11 81 81 88 88 90 90 99 99 A0 A9 B1 B8 | |||
12 81 88 90 99 A0 A0 A9 A9 B1 B8 B1 B8 | |||
13 81 88 90 99 A0 A0 A9 A9 B1 B8 B1 B8 | |||
14 81 88 90 99 A0 A9 B1 B8 B1 B8 B1 B8 | |||
15 81 81 88 88 90 90 99 99 A0 A9 B1 B8 | |||
16 81 88 90 99 A0 A0 A9 A9 B1 B1 B8 B8 | |||
17 81 88 90 99 A0 A0 A9 A9 B1 B1 B8 B8 | |||
18 81 88 90 99 A0 A9 B1 B8 B1 B1 B8 B8 | |||
19 81 81 88 88 90 90 99 99 A0 A9 B1 B8 | |||
1A 81 88 90 99 A0 A0 A9 A9 B1 B8 B1 B8 | |||
1B 81 88 90 99 A0 A0 A9 A9 B1 B8 B1 B8 | |||
1C 81 88 90 99 A0 A9 B1 B8 B1 B8 B1 B8 | |||
1D 81 81 88 88 90 90 99 99 A0 A9 B1 B8 | |||
1E 81 88 90 99 A0 A0 A9 A9 B1 B1 B8 B8 | |||
1F 81 88 90 99 A0 A0 A9 A9 B1 B1 B8 B8 | |||
20 81 88 90 99 A0 A9 B1 B8 70 71 78 79 | |||
21 80 81 88 89 90 91 98 99 60 69 71 78 | |||
22 81 88 90 99 A0 A1 A8 A9 71 78 71 78 | |||
23 81 88 90 99 A0 A1 A8 A9 70 78 71 79 | |||
24 81 88 90 99 A0 A9 B1 B8 70 78 71 79 | |||
25 80 81 88 89 90 91 98 99 60 69 71 78 | |||
26 81 88 90 99 A0 A1 A8 A9 71 71 78 78 | |||
27 81 88 90 99 A0 A1 A8 A9 70 71 78 79 | |||
28 81 88 90 99 A0 A9 B1 B8 70 70 78 78 | |||
29 80 81 88 89 90 91 98 99 60 69 71 78 | |||
2A 81 88 90 99 A0 A1 A8 A9 71 78 71 78 | |||
2B 81 88 90 99 A0 A1 A8 A9 71 79 71 79 | |||
2C 81 88 90 99 A0 A9 B1 B8 71 79 71 79 | |||
2D 80 81 88 89 90 91 98 99 60 69 71 78 | |||
2E 81 88 90 99 A0 A1 A8 A9 71 71 78 78 | |||
2F 81 88 90 99 A0 A1 A8 A9 70 70 78 78 | |||
30 81 88 90 99 A0 A9 B1 B8 B0 B1 B8 B9 | |||
31 80 81 88 89 90 91 98 99 A0 A9 B1 B8 | |||
32 81 88 90 99 A0 A1 A8 A9 B1 B8 B1 B8 | |||
33 81 88 90 99 A0 A1 A8 A9 B0 B8 B1 B9 | |||
34 81 88 90 99 A0 A9 B1 B8 B0 B8 B1 B9 | |||
35 80 81 88 89 90 91 98 99 A0 A9 B1 B8 | |||
36 81 88 90 99 A0 A1 A8 A9 B1 B1 B8 B8 | |||
37 81 88 90 99 A0 A1 A8 A9 B0 B1 B8 B9 | |||
38 81 88 90 99 A0 A9 B1 B8 B0 B0 B8 B8 | |||
39 80 81 88 89 90 91 98 99 A0 A9 B1 B8 | |||
3A 81 88 90 99 A0 A1 A8 A9 B1 B8 B1 B8 | |||
3B 81 88 90 99 A0 A1 A8 A9 B1 B9 B1 B9 | |||
3C 81 88 90 99 A0 A9 B1 B8 B1 B9 B1 B9 | |||
3D 80 81 88 89 90 91 98 99 A0 A9 B1 B8 | |||
3E 81 88 90 99 A0 A1 A8 A9 B1 B1 B8 B8 | |||
3F 81 88 90 99 A0 A1 A8 A9 B0 B0 B8 B8 | |||
The registers from D000 through E003 contained the pattern 01/08/10/19/20/29/31/38. | |||
The $40s bit in this table is the CHRROM /OE. The $80s bit in this table is the CIRAM /OE. | |||
(Thus, values from $80-$BF are from ROM and values from $40-$7F are from RAM. Other values are not present (fortunately) —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 17:57, 23 January 2014 (MST) | |||
Revision as of 00:57, 24 January 2014
Extended VRC6 PPU banking modes
The VRC6 documentation (currently linked from here) seems to indicate that register $B003 has quite a lot more bits than we currently know about:
- D0/D1: CHR/NT Bank mode
- mode 0 - normal
- mode 1 - regs 0-3 select 2KB CHR banks, regs 4-7 select nametable banks
- mode 2 - regs 0-3 select 1KB CHR banks at 0000-0FFF, regs 4-5 select 2KB CHR banks at 1000-1FFF, regs 6-7 select nametable banks (controlled by mirroring)
- mode 3 - pattern tables seemingly also get mapped into the nametables?
- D2/D3: mirroring control
- D4: 0 = Use extra 8KB CHR RAM for nametables (in bank modes 1-3); 1 = Use CHR ROM for nametables
- D5: something related to CHR ROM?
- D7: SRAM enable (1 = enable)
--Quietust (talk) 09:07, 23 October 2013 (MDT)
- That's funny- I noticed something related when I was reformatting up the VRC6 pinout page, pin 32.—Lidnariq (talk) 13:54, 23 October 2013 (MDT)
Raw data
Here's the raw data I received from BootGod that I used to determine the exact banking pattern of the VRC6:
b003 0000 0400 0800 0c00 1000 1400 1800 1c00 2000 2400 2800 2c00 00 81 88 90 99 A0 A9 B1 B8 71 71 78 78 01 81 81 88 88 90 90 99 99 60 69 71 78 02 81 88 90 99 A0 A0 A9 A9 71 78 71 78 03 81 88 90 99 A0 A0 A9 A9 71 78 71 78 04 81 88 90 99 A0 A9 B1 B8 71 78 71 78 05 81 81 88 88 90 90 99 99 60 69 71 78 06 81 88 90 99 A0 A0 A9 A9 71 71 78 78 07 81 88 90 99 A0 A0 A9 A9 71 71 78 78 08 81 88 90 99 A0 A9 B1 B8 71 71 78 78 09 81 81 88 88 90 90 99 99 60 69 71 78 0A 81 88 90 99 A0 A0 A9 A9 71 78 71 78 0B 81 88 90 99 A0 A0 A9 A9 71 78 71 78 0C 81 88 90 99 A0 A9 B1 B8 71 78 71 78 0D 81 81 88 88 90 90 99 99 60 69 71 78 0E 81 88 90 99 A0 A0 A9 A9 71 71 78 78 0F 81 88 90 99 A0 A0 A9 A9 71 71 78 78 10 81 88 90 99 A0 A9 B1 B8 B1 B1 B8 B8 11 81 81 88 88 90 90 99 99 A0 A9 B1 B8 12 81 88 90 99 A0 A0 A9 A9 B1 B8 B1 B8 13 81 88 90 99 A0 A0 A9 A9 B1 B8 B1 B8 14 81 88 90 99 A0 A9 B1 B8 B1 B8 B1 B8 15 81 81 88 88 90 90 99 99 A0 A9 B1 B8 16 81 88 90 99 A0 A0 A9 A9 B1 B1 B8 B8 17 81 88 90 99 A0 A0 A9 A9 B1 B1 B8 B8 18 81 88 90 99 A0 A9 B1 B8 B1 B1 B8 B8 19 81 81 88 88 90 90 99 99 A0 A9 B1 B8 1A 81 88 90 99 A0 A0 A9 A9 B1 B8 B1 B8 1B 81 88 90 99 A0 A0 A9 A9 B1 B8 B1 B8 1C 81 88 90 99 A0 A9 B1 B8 B1 B8 B1 B8 1D 81 81 88 88 90 90 99 99 A0 A9 B1 B8 1E 81 88 90 99 A0 A0 A9 A9 B1 B1 B8 B8 1F 81 88 90 99 A0 A0 A9 A9 B1 B1 B8 B8 20 81 88 90 99 A0 A9 B1 B8 70 71 78 79 21 80 81 88 89 90 91 98 99 60 69 71 78 22 81 88 90 99 A0 A1 A8 A9 71 78 71 78 23 81 88 90 99 A0 A1 A8 A9 70 78 71 79 24 81 88 90 99 A0 A9 B1 B8 70 78 71 79 25 80 81 88 89 90 91 98 99 60 69 71 78 26 81 88 90 99 A0 A1 A8 A9 71 71 78 78 27 81 88 90 99 A0 A1 A8 A9 70 71 78 79 28 81 88 90 99 A0 A9 B1 B8 70 70 78 78 29 80 81 88 89 90 91 98 99 60 69 71 78 2A 81 88 90 99 A0 A1 A8 A9 71 78 71 78 2B 81 88 90 99 A0 A1 A8 A9 71 79 71 79 2C 81 88 90 99 A0 A9 B1 B8 71 79 71 79 2D 80 81 88 89 90 91 98 99 60 69 71 78 2E 81 88 90 99 A0 A1 A8 A9 71 71 78 78 2F 81 88 90 99 A0 A1 A8 A9 70 70 78 78 30 81 88 90 99 A0 A9 B1 B8 B0 B1 B8 B9 31 80 81 88 89 90 91 98 99 A0 A9 B1 B8 32 81 88 90 99 A0 A1 A8 A9 B1 B8 B1 B8 33 81 88 90 99 A0 A1 A8 A9 B0 B8 B1 B9 34 81 88 90 99 A0 A9 B1 B8 B0 B8 B1 B9 35 80 81 88 89 90 91 98 99 A0 A9 B1 B8 36 81 88 90 99 A0 A1 A8 A9 B1 B1 B8 B8 37 81 88 90 99 A0 A1 A8 A9 B0 B1 B8 B9 38 81 88 90 99 A0 A9 B1 B8 B0 B0 B8 B8 39 80 81 88 89 90 91 98 99 A0 A9 B1 B8 3A 81 88 90 99 A0 A1 A8 A9 B1 B8 B1 B8 3B 81 88 90 99 A0 A1 A8 A9 B1 B9 B1 B9 3C 81 88 90 99 A0 A9 B1 B8 B1 B9 B1 B9 3D 80 81 88 89 90 91 98 99 A0 A9 B1 B8 3E 81 88 90 99 A0 A1 A8 A9 B1 B1 B8 B8 3F 81 88 90 99 A0 A1 A8 A9 B0 B0 B8 B8
The registers from D000 through E003 contained the pattern 01/08/10/19/20/29/31/38.
The $40s bit in this table is the CHRROM /OE. The $80s bit in this table is the CIRAM /OE.
(Thus, values from $80-$BF are from ROM and values from $40-$7F are from RAM. Other values are not present (fortunately) —Lidnariq (talk) 17:57, 23 January 2014 (MST)
