Talk:VRC6: Difference between revisions
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* D7: SRAM enable (1 = enable) | * D7: SRAM enable (1 = enable) | ||
--[[User:Quietust|Quietust]] ([[User talk:Quietust|talk]]) 09:07, 23 October 2013 (MDT) | --[[User:Quietust|Quietust]] ([[User talk:Quietust|talk]]) 09:07, 23 October 2013 (MDT) | ||
: That's funny- I noticed something related when I was reformatting up the [[VRC6 pinout]] page, pin 32.—[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 13:54, 23 October 2013 (MDT) | |||
Revision as of 19:54, 23 October 2013
The VRC6 documentation (currently linked from here) seems to indicate that register $B003 has quite a lot more bits than we currently know about:
- D0/D1: CHR/NT Bank mode
- mode 0 - normal
- mode 1 - regs 0-3 select 2KB CHR banks, regs 4-7 select nametable banks
- mode 2 - regs 0-3 select 1KB CHR banks at 0000-0FFF, regs 4-5 select 2KB CHR banks at 1000-1FFF, regs 6-7 select nametable banks (controlled by mirroring)
- mode 3 - pattern tables seemingly also get mapped into the nametables?
- D2/D3: mirroring control
- D4: 0 = Use extra 8KB CHR RAM for nametables (in bank modes 1-3); 1 = Use CHR ROM for nametables
- D5: something related to CHR ROM?
- D7: SRAM enable (1 = enable)
--Quietust (talk) 09:07, 23 October 2013 (MDT)
- That's funny- I noticed something related when I was reformatting up the VRC6 pinout page, pin 32.—Lidnariq (talk) 13:54, 23 October 2013 (MDT)
