Talk:Mirroring

PAxx vs. PPU Axx vs. CHR Axx

These edits by infiniteneslives confuse me a bit. I've seen "CHR A10" and "CHR A11" used for the lines going to the CHR ROM. In ASIC mappers, these tend not to match PPU A10 (PA10 for short) and PPU A11 (PA11). --Tepples (talk) 12:04, 23 February 2013 (MST)

"L" mirroring

Using a single and-or-invert gate, or three NAND or NOR gates, along with two bits from a latch gets you controllable 1/H/V/L mirroring. This is roughly what mapper 243 does. —Lidnariq (talk) 00:32, 4 May 2013 (MDT)

4-screen capable mappers

lidnariq wrote here:

None of MMC3, MMC5, m77, nor m99 "are capable of mapping some of their CHR[...] into the nametable space". The question of CHR as nametables is largely orthogonal to 4-screen layout; I don't think it belongs here.

I think any mapper that can map 4 different 1k pages into the 4 nametable regions is relevant to 4-screen mirroring (this is what I consider the definition of 4-screen mirroring). Why don't you think they belong there?

• MMC3 - Rad Racer 2.
• MMC5 - Using fill-mode as a 4th nametable qualifies, I think, but is very limited.
• VRC6 - Lets you map CHR-ROM into nametable pages arbitrarily. (Not sure if any games do it.)
• Namco 163 - Lets you map CHR-ROM into nametable pages arbitrarily. (See Final Lap.)
• iNES Mapper 077 - Uses combination of VRAM and CHR-RAM to create 4 RAM nametables. (Napoleon Senki)
• iNES Mapper 099 - Not sure why this became a mapper, but as described I don't see why it doesn't qualify as 4-screen capable?

- Rainwarrior (talk) 10:42, 14 May 2015 (MDT)

The sentence discusses mapping some of their CHR into the nametable space. Which is false for four of the examples, and orthogonal to how four-screen mirroring works. If rephrased to instead be what actually belongs in the section ("allows treating nametable address space as a 64x60 tile map") it's then redundant with the surrounding text. (MMC5 supports three real nametables and a fourth where all 960 locations are the same tile and same attribute... which I personally wouldn't count here) —Lidnariq (talk) 10:58, 14 May 2015 (MDT)

I don't think it's orthogonal at all! What do you mean by this? Mapping CHR-RAM or CHR-ROM into the nametable space is one way of implementing 4-screen mirroring. I've separated MMC5 and the Vs mapper. VRC6, N163, and 77 all map their CHR-RAM or ROM chips directly into the nametable space, so I don't know which four examples you think are false; at most it would just be MMC3? I thought Rad Racer 2 mapped CHR-ROM as nametables, but I would have to check again. - Rainwarrior (talk) 11:07, 14 May 2015 (MDT)

CHR is stored on memory. Memory itself is not CHR. That Napoleon Senki uses one 8 KiB RAM that's used for both two nametables and for 6 KiB of CHR-RAM doesn't mean that the CHR is mapped into the nametables. Additionally, I say it's orthogonal because you don't mention JY Company or Sunsoft 4 in this section (but instead mention them in the "other" section).

If you replace "CHR" with "on-cartridge PPU memory" then this specific sentence is redundant with the surrounding text: "MMC3" is redundant with "Add a 6264 8 KB RAM on the board. CIRAM /CE is pulled high, and the cartridge RAM is enabled at $2000-$3FFF. The PPU itself never uses $3000-$3FFF during rendering, but 8 KB RAMs are easier to find than 4 KB RAMs.". The missing "MIMIC-1" is redundant with "Add an extra 2 KB of RAM on the board. Decoder logic enables CIRAM only for $2000-$27FF and the cartridge RAM $2800-$2FFF.". Mapper 77 is repeated in the list below. —Lidnariq (talk) 11:18, 14 May 2015 (MDT)