Talk:MMC3 pinout: Difference between revisions
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[[User:Bregalad|Bregalad]] ([[User talk:Bregalad|talk]]) 05:55, 5 October 2018 (MDT) | [[User:Bregalad|Bregalad]] ([[User talk:Bregalad|talk]]) 05:55, 5 October 2018 (MDT) | ||
: The alternatives all look worse to me.—[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 10:46, 5 October 2018 (MDT) | : The alternatives all look worse to me.—[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 10:46, 5 October 2018 (MDT) | ||
== PRG RAM /CE and PRG RAM +CE == | |||
How PRG RAM +CE works? Is it just inverted PRG RAM /CE? Or it's controlled via the $A001 register while PRG RAM /CE is low when $6000-$7FFF addressed? [[User:Cluster|Cluster]] ([[User talk:Cluster|talk]]) 19:03, 8 August 2021 (UTC) | |||
:I am pretty sure (but not confirmed) +CE is being controlled by $A001 bits 6 and 7, and /CE is being controlled by the CPU address bus range $6000-7FFF. (/ROMSEL, A14, A13 = 1,1,1) [[User:Ben Boldt|Ben Boldt]] ([[User talk:Ben Boldt|talk]]) 19:08, 8 August 2021 (UTC) | |||
::Furrtek's reverse-engineered schematic from the die shots of the ULA [https://github.com/furrtek/VGChips/tree/master/Nintendo/MMC3C] show that pin is just /RD... but I checked on an MMC3A and MMC3B and pin 30 connects to RAM pin 20 - -CE; and RAM pin 22 is grounded. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 04:43, 22 August 2021 (UTC) | |||
Latest revision as of 04:43, 22 August 2021
Pinout with chip rotated 45°
No offense but the pinout with the chip rotated 45° by Lidnariq in july 2012 looks awful in my personal opinion. (How could it go unnoticed by me for 6 years ?!) Bregalad (talk) 05:55, 5 October 2018 (MDT)
PRG RAM /CE and PRG RAM +CE
How PRG RAM +CE works? Is it just inverted PRG RAM /CE? Or it's controlled via the $A001 register while PRG RAM /CE is low when $6000-$7FFF addressed? Cluster (talk) 19:03, 8 August 2021 (UTC)
