Talk:APU/current: Difference between revisions
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But my understanding is the triangle, noise, and DMC timers are clocked on every CPU cycle, and only the pulse channel timers are clocked on every second CPU cycle. Have I understood correctly? --[[User:Bavi H|Bavi H]] ([[User talk:Bavi H|talk]]) 21:29, 19 February 2014 (MST) | But my understanding is the triangle, noise, and DMC timers are clocked on every CPU cycle, and only the pulse channel timers are clocked on every second CPU cycle. Have I understood correctly? --[[User:Bavi H|Bavi H]] ([[User talk:Bavi H|talk]]) 21:29, 19 February 2014 (MST) | ||
:Then why do noise and DMC timers produce only even periods? --[[User:Tepples|Tepples]] ([[User talk:Tepples|talk]]) 07:22, 20 February 2014 (MST) | |||
Revision as of 14:22, 20 February 2014
Looking at Visual 2A03 and e.g. the sq0_on and sq0_len nodes, it seems that disabling a channel doesn't touch the length counter at all. Rather, there are internal channel enable flags (eg. sq0_on) that get set when the length counter is initialized (presumably only for non-zero values, though I haven't checked) and cleared when either the length counter reaches zero or the channel is disabled. These are the flags you get back from $4015/read as well. Even if this page only describes "abstract APU operation", that's not any more complicated than the current version, so maybe the descriptions should be updated. -Ulfalizer (talk) 23:30, 28 April 2013 (MDT)
Glossary entry for "timer"
The glossary entry for timer says
The triangle channel's timer is clocked on every CPU cycle, but the pulse, noise, and DMC timers are clocked only on every second CPU cycle and thus produce only even periods.
But my understanding is the triangle, noise, and DMC timers are clocked on every CPU cycle, and only the pulse channel timers are clocked on every second CPU cycle. Have I understood correctly? --Bavi H (talk) 21:29, 19 February 2014 (MST)
