CPU addressing modes: Difference between revisions
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The NES CPU is a second-source version of MOS Technology 6502, manufactured by Ricoh. | The NES CPU is a second-source version of MOS Technology 6502, manufactured by Ricoh. | ||
Addressing modes and instruction timings are the same as those in the standard 6502. | Addressing modes and instruction timings are the same as those in the standard 6502. | ||
This page summarizes the 6502 addressing modes and explains some cases where certain modes might be useful. | |||
== Indexed addressing == | == Indexed addressing == | ||
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The (d),y mode is used far more often than (d,x). | The (d),y mode is used far more often than (d,x). | ||
The latter implies a table of addresses on zero page, and that's rarely used except perhaps in a music engine, where X has the possibility of being 0, 4, 8, or 12. | The latter implies a table of addresses on zero page, and that's rarely used except perhaps in a music engine, where X has the possibility of being 0, 4, 8, or 12 to match [[APU]] register offsets. | ||
Revision as of 14:02, 17 March 2010
The NES CPU is a second-source version of MOS Technology 6502, manufactured by Ricoh. Addressing modes and instruction timings are the same as those in the standard 6502.
This page summarizes the 6502 addressing modes and explains some cases where certain modes might be useful.
Indexed addressing
The 6502 has six main indexed addressing modes:
| Abbr | Name | Formula | Cycles |
|---|---|---|---|
| d,x | Absolute indexed | 4 | |
| d,y | Absolute indexed | 4 | |
| a,x | Absolute indexed | 4+ | |
| a,y | Absolute indexed | 4+ | |
| (d,x) | Indirect | val = PEEK(PEEK((arg + X) % 256) + PEEK((arg + X + 1) % 256) * 256) | |
| (d),y | Indirect | 5+ |
Notes:
- Abbreviations for addressing modes are those used in WDC's 65C816 data sheets.
- + means add a cycle for write instructions or for page wrapping on read instructions, called the "oops" cycle below.
The 6502 has one 8-bit ALU and one 16-bit upcounter (for PC). To calculate a,x or a,y addressing in an instruction other than sta, stx, or sty, it uses the 8-bit ALU to first calculate the low byte while it fetches the high byte. If there's a carry out, it goes "oops", applies the carry using the ALU, and repeats the read at the correct address. Store instructions always have this "oops" cycle: the CPU first reads from the partially added address and then writes to the correct address. The same thing happens on (d),y indirect addressing.
The (d),y mode is used far more often than (d,x). The latter implies a table of addresses on zero page, and that's rarely used except perhaps in a music engine, where X has the possibility of being 0, 4, 8, or 12 to match APU register offsets.
