VRC3 pinout: Difference between revisions
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[[Category:Pinouts]][[VRC3]]: 18-pin PDIP ( | [[Category:Pinouts]][[VRC3]]: 18-pin PDIP ('''mapper 73''') | ||
r: connects to PRG ROM | r: connects to PRG ROM | ||
Revision as of 06:02, 5 May 2014
VRC3: 18-pin PDIP (mapper 73)
r: connects to PRG ROM
f: connects to Famicom
w: connects to PRG RAM
.-\_/-.
(r) PRG A16 <- |01 18| -- +5V
(r) PRG /CE <- |02 17| -> WRAM /CE (w)
(r) PRG A14 <- |03 16| <- CPU RnW (wfr)
(r) PRG A15 <- |04 15| <- CPU D3 (wfr)
(f) CPU M2 -> |05 14| <- CPU D0 (wfr)
(wfr) CPU A12 -> |06 13| <- CPU D1 (wfr)
(rf) CPU A13 -> |07 12| <- CPU D2 (wfr)
(f) CPU A14 -> |08 11| <- nROMSEL (f)
Gnd -- |09 10| -> nIRQ (f)
'-----'
