VRC2 pinout: Difference between revisions

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m (... integrate information in http://nesdev.parodius.com/bbs/viewtopic.php?t=8569)
m (replace PRG and CHR with CPU and PPU when appropriate; remove extra spaces; remove certainly-wrong "CHR A18")
Line 5: Line 5:
* (r) this only connects to the ROM  
* (r) this only connects to the ROM  
* (n) means this pin is connected to the NES only  
* (n) means this pin is connected to the NES only  
* CHR : these connect to the CHR ROM and/or fami's CHR pins
* CHR : these connect to the CHR ROM
* PRG : these connect to the PRG ROM and/or fami's PRG pins
* PPU : these connect to the PPU
 
* PRG : these connect to the PRG ROM
                                  .----\/----.  
* CPU : these connect to the CPU
                    (n) PRG A13 -> |01     40| - +5V
                  .--\/--.  
                    (n) PRG A14 -> |02     39| -> PRG A17 (r)
    (n) CPU A13 -> |01 40| -- +5V
                    (s) PRG A1 -> |03     38| -> PRG A15 (r)
    (n) CPU A14 -> |02 39| -> PRG A17 (r)
                    (s) PRG A0 -> |04     37| <- PRG A12 (s)
    (s) CPU A1 -> |03 38| -> PRG A15 (r)
                    (n) CHR A12 -> |05     36| -> PRG A14 (r)
    (s) CPU A0 -> |04 37| <- CPU A12 (s)
                    (n) CHR A11 -> |06     35| -> PRG A13 (r)
    (n) PPU A12 -> |05 36| -> PRG A14 (r)
                    (n) CHR A10 -> |07     34| -> PRG A16 (r)
    (n) PPU A11 -> |06 35| -> PRG A13 (r)
                    (r) PRG /CE <- |08     33| <- PRG D0 (s)
    (n) PPU A10 -> |07 34| -> PRG A16 (r)
                    (n) PRG R/W -> |09     32| <- PRG D1 (s)
    (r) PRG /CE <- |08 33| <- CPU D0 (s)
                    (r) CHR /CE <- |10     31| <- PRG D2 (s)
    (n) CPU R/W -> |09 32| <- CPU D1 (s)
                    (n) CHR A13 -> |11     30| <- PRG D4 (s)
    (r) CHR /CE <- |10 31| <- CPU D2 (s)
                    (n) CHR /OE -> |12     29| <- PRG D3 (s)
    (n) PPU A13 -> |11 30| <- CPU D4 (s)
                    (n) CHR A10 -> |13     28| -> CHR A17 (r)
    (n) PPU /OE -> |12 29| <- CPU D3 (s)
                    (n) PRG /CE -> |14     27| -> CHR A15 (r)
    (n) PPU A10 -> |13 28| -> CHR A17 (r)
                        (n) M2 -> |15     26| -> CHR A12 (r)
    (n) /ROMSEL -> |14 27| -> CHR A15 (r)
              VRC4 (r) CHR A18 <- |16     25| -> CHR A14 (r)
        (n) M2 -> |15 26| -> CHR A12 (r)
                  VRC4 (n) /IRQ <- |17     24| -> CHR A13 (r)
              ? -- |16 25| -> CHR A14 (r)
                            NC - |18     23| -> CHR A11 (r)
  VRC4 (n) /IRQ <- |17 24| -> CHR A13 (r)
                  VRC4 WRAM /CE <- |19     22| -> CHR A16 (r)
              ? -- |18 23| -> CHR A11 (r)
                            GND - |20     21| -> CHR A10 (r)
  VRC4 WRAM /CE <- |19 22| -> CHR A16 (r)
                                  `----------'
            GND -- |20 21| -> CHR A10 (r)
                  `------'


On the VRC2, pins 16-19 seem to have been [http://nesdev.parodius.com/bbs/viewtopic.php?t=8569 intended for a never-seen-used EEPROM]
On the VRC2, pins 16-19 seem to have been [http://nesdev.parodius.com/bbs/viewtopic.php?t=8569 intended for a never-seen-used EEPROM]

Revision as of 06:47, 21 August 2012

The Konami VRC2 and VRC4 chips come in almost-identical 40-pin DIP packages :


  • (s) means this pin is shared between rom, system and NES
  • (r) this only connects to the ROM
  • (n) means this pin is connected to the NES only
  • CHR : these connect to the CHR ROM
  • PPU : these connect to the PPU
  • PRG : these connect to the PRG ROM
  • CPU : these connect to the CPU
                  .--\/--. 
   (n) CPU A13 -> |01  40| -- +5V
   (n) CPU A14 -> |02  39| -> PRG A17 (r)
    (s) CPU A1 -> |03  38| -> PRG A15 (r)
    (s) CPU A0 -> |04  37| <- CPU A12 (s)
   (n) PPU A12 -> |05  36| -> PRG A14 (r)
   (n) PPU A11 -> |06  35| -> PRG A13 (r)
   (n) PPU A10 -> |07  34| -> PRG A16 (r)
   (r) PRG /CE <- |08  33| <- CPU D0 (s)
   (n) CPU R/W -> |09  32| <- CPU D1 (s)
   (r) CHR /CE <- |10  31| <- CPU D2 (s)
   (n) PPU A13 -> |11  30| <- CPU D4 (s)
   (n) PPU /OE -> |12  29| <- CPU D3 (s)
   (n) PPU A10 -> |13  28| -> CHR A17 (r)
   (n) /ROMSEL -> |14  27| -> CHR A15 (r)
        (n) M2 -> |15  26| -> CHR A12 (r)
             ? -- |16  25| -> CHR A14 (r)
 VRC4 (n) /IRQ <- |17  24| -> CHR A13 (r)
             ? -- |18  23| -> CHR A11 (r)
 VRC4 WRAM /CE <- |19  22| -> CHR A16 (r)
           GND -- |20  21| -> CHR A10 (r)
                  `------'

On the VRC2, pins 16-19 seem to have been intended for a never-seen-used EEPROM

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