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| [[Category:ASIC mappers]][[Category:Mappers with scanline IRQs]][[Category:MMC3-like mappers]] | | #REDIRECT [[NES 2.0 Mapper 268]] |
| UNIF MAPR '''COOLBOY''' describes a mapper designed for [[MMC3]] multicarts. Unlike almost all other mappers, it is currently being manufactured. (Search for "COOLBOY" on eBay or AliExpress).
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| It adds four extra registers in lieu of (in addition to?) the normal PRG-RAM. FCEUX claims that all four of these registers are cleared on power up and reset.
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| == Registers ==
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| These registers overlay, but are independent from, any PRG-RAM present.
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| Mask: $E003
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| === $6000 ===
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| 7 bit 0
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| ---- ----
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| ABCC DEEE
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| |||| ||||
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| |||| |+++-- PRG offset (PRG A19, A18, A17)
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| |||| +----- Alternate CHR A17
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| ||++------- PRG offset (PRG A24, A23)
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| |+--------- PRG mask (PRG A17 from 0: MMC3; 1: offset)
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| +---------- CHR mask (CHR A17 from 0: MMC3; 1: alternate)
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| === $6001 ===
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| 7 bit 0
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| ---- ----
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| GHIJ KKLx
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| |||| ||+--- GNROM mode bank PRG size (1: 32 KiB bank, PRG A14=CPU A14; 0: 16 KiB bank, PRG A14=offset A14)
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| |||+-++---- PRG offset (in order: PRG A20, A22, A21)
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| ||+-------- PRG mask (PRG A19 from 0: offset; 1: MMC3)
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| |+--------- PRG mask (PRG A18 from 0: MMC3; 1: offset)
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| +---------- PRG mask (PRG A20 from 0: offset; 1: MMC3)
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| === $6002 ===
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| 7 bit 0
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| ---- ----
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| xxxx MMMM
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| ++++-- CHR offset for GNROM mode (CHR A16, A15, A14, A13)
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| === $6003 ===
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| 7 bit 0
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| ---- ----
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| NPxP QQRx
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| || | +++--- PRG offset for GNROM mode (PRG A16, A15, A14)
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| || +------- 1: GNROM mode; 0: MMC3 mode
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| || | (1: PRG A16, A15 from QQ + PRG A14 from L, R, and CPU A14 + CHR A16...13 from MMMM + CHR A12...10 from PPU A12...10;
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| || | 0: PRG A16, A15, A14, A13 from MMC3 + CHR A16...A10 from MMC3 )
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| |+-+------- Banking mode
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| |+--------- "Weird MMC3 mode"
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| +---------- Lockout (prevent further writes to these four registers, only works in MMC3 mode)
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| == Register interpretation ==
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| The following things are always true, regardless of mode:
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| * The CCKK bits are always connected to PRG A24..A21.
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| * The PRG and CHR mask controls (B, G, H, I, & A) always control whether PRG A20..A17 and CHR A17 are connected to the internal MMC3 registers, or the literal values in other controls (J, EEE, & D).
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| === Banking mode = $00 ===
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| “Normal” oversize MMC3 mode.
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| Supports MMC3 anywhere between 128 KiB and 2 MiB, otherwise identical to ordinary [[MMC3]]. Goofy mask values will produce goofy memory layouts.
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| The combined register of CCKKJEEE could be thought of as a way to select one of 256 different 128 KiB PRG MMC3 games, or CCKK selecting one of 16 different 2 MiB MMC3 games.
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| Lockout works in this mode.
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| === Banking mode = $10 ===
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| “Normal” GNROM mode.
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| PRG A16 and A15 come from the QQ controls.
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| When in 16 KiB PRG mode (L control), PRG A14 comes from the R control. Otherwise, it comes from CPU A14.
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| CHR A16, A15, A14, and A13 come from MMMM controls. CHR A12, A11, and A10 come from PPU A12, A11, and A10.
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| The combined register of CCKKJEEEQQR could be thought of as a way to select one of 2048 different 16 KiB NROM games.
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| Note: The CHR and PRG mask registers STILL AFFECT THIS MODE, allowing weird splicing of MMC3 banking (with 128 KiB granularity) overlaying GNROM-style banking.
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| Lockout DOES NOT work in this mode.
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| === Banking mode = $40 ===
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| “Weird” MMC3 mode.
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| If [[MMC3#Bank select .28.248000-.249FFE.2C even.29|MMC3 PRG ROM bank mode]] is "normal" (8+8+16F), then the PRG banks at 0xC000 and 0xE000 are fixed to 8 KiB bank 0, instead of 0xFE and 0xFF. Supposedly this effect is completely ignored when MMC3 PRG ROM bank mode is inverted (8F+8+8+8F).
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| The second half of each of the 2 KiB CHR banks is replaced with bank 0, and the LSB of MMC3 registers 0 and 1 work (instead of being replaced by PPU A10).
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| Otherwise, behaves as “normal” MMC3 mode above.
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| === Banking mode = $50 ===
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| “Weird” GNROM-ish mode.
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| Combine the rules mentioned above for “Normal” GNROM mode with “Weird” MMC3 mode. (These descriptions should not be contradictory.)
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| Lockout DOES NOT work in this mode.
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