Taito X1-017 pinout

Taito X1-017: 64-pin 0.6" shrink DIP (Canonically mapper 82)

                 .---\/---.
  (r) PRG A16 <- |01    64| -- VCC
 (fw) CPU A13 -> |02    63| <- M2 (f)
 (frw) PRG A8 -> |03    62| -> (PRG)
 (frw) PRG A7 -> |04    61| -> PRG A13 (r)
 (frw) PRG A9 -> |05    60| -> (PRG)
 (fw) CPU A14 -> |06    59| -> PRG A14 (r)
(frw) PRG A11 -> |07    58| -> PRG A15 (r)
 (frw) PRG A6 -> |08    57| <- PRG A12 (frw)
 (frw) PRG A5 -> |09    56| -- BRIDGED TO PIN 46 (C3+R2 MAYBE VCC IN)
(frw) PRG A10 -> |10    55| -> delayed M2
 (frw) PRG A4 -> |11    54| -> modified M2 (only rising edge delayed)
 (frw) PRG A3 -> |12    53| <- PRG RAM +CE (jumpered to pin 55 by default)
 (frw) PRG D7 <> |13    52| -- VCC
 (frw) PRG A2 -> |14    51| -- GND
 (frw) PRG D6 <> |15    50| -- PAD2 (NC)
 (frw) PRG A1 -> |16    49| -- VBAT
 (frw) PRG D5 <> |17    48| -- RAM VCC
 (frw) PRG A0 -> |18    47| -- GND
 (frw) PRG D4 <> |19    46| -- BRIDGED TO PIN 56 (C3+R2 MAYBE VCC IN)
 (frw) PRG D0 <> |20    45| -- NC
 (frw) PRG D3 <> |21    44| -- NC
 (frw) PRG D1 <> |22    43| -- GND
 (frw) PRG D2 <> |23    42| -> CHR A11 (r)
  (f) CPU R/W -> |24    41| -> CIRAM A10 (f)
 (fr) /ROMSEL -> |25    40| -> CHR A17 (r) 
     (f) /IRQ <- |26    39| <- PPU A10 (f)
          GND -- |27    38| -> CHR A16 (r)
 (fr) PPU /OE -> |28    37| <- PPU A11 (f)
  (r) CHR A15 <- |29    36| -> CHR A10 (r)
  (r) CHR A14 <- |30    35| <- PPU A12 (f)
  (r) CHR A13 <- |31    34| -- NC
  (r) CHR A12 <- |32    33| <- PPU A13 (fr)
                 '--------'

Pins 60 and 62 are PRG banking pins corresponding to the two least significant bits written to the PRG banking registers. [1] However, the OEM wiring skips them.

Note that PCBs that use a 28 pin 128KiB Mask ROM for PRG shuffle A13, A14, A15, and A16. [2]

Source: Ice Man's forum post