SxROM: Difference between revisions
From NESdev Wiki
Jump to navigationJump to search
(→Higher CHR lines: Better wording for SOROM / SZROM.) |
(→Higher CHR lines: and then you threw away the information as to which chip was the battery-backed one. Additionally, SOROM was never found with SL1 shorted and all the switchover components missing, so don't repeat that possibility.) |
||
| Line 79: | Line 79: | ||
*SNROM uses the upper CHR bank select line coming out of the mapper (CHR A16; bit 4 of bank number) as an additional chip enable for the PRG RAM.[http://forums.nesdev.org/viewtopic.php?t=7045] All other boards with PRG RAM appear to tie /CE to ground. | *SNROM uses the upper CHR bank select line coming out of the mapper (CHR A16; bit 4 of bank number) as an additional chip enable for the PRG RAM.[http://forums.nesdev.org/viewtopic.php?t=7045] All other boards with PRG RAM appear to tie /CE to ground. | ||
*SUROM uses CHR A16 to control the upper address line (PRG A18) of its 512KB PRG ROM. | *SUROM uses CHR A16 to control the upper address line (PRG A18) of its 512KB PRG ROM. | ||
*SOROM uses a similar method, using the second-highest CHR bank select line to choose between two 8KB PRG RAM chips. Only | *SOROM uses a similar method, using the second-highest CHR bank select line to choose between two 8KB PRG RAM chips. Only the RAM chip selected by driving CHR A15 high is battery backed. | ||
*SXROM is a combination of SOROM and SUROM, addressing both 512KB of PRG ROM and 32KB of PRG RAM. | *SXROM is a combination of SOROM and SUROM, addressing both 512KB of PRG ROM and 32KB of PRG RAM. | ||
*SZROM retains multiple address lines for CHR ROM banking, but also has 16 KiB of PRG RAM. It uses CHR A16, instead of SOROM's CHR A15, to select between two 8 KiB PRG RAM chips. | *SZROM retains multiple address lines for CHR ROM banking, but also has 16 KiB of PRG RAM. It uses CHR A16, instead of SOROM's CHR A15, to select between two 8 KiB PRG RAM chips. Similar to SOROM, only the RAM chip selected by driving CHR A16 high is battery backed. | ||
In these scenarios, however, both CHR bank registers must be set to the same value (or the CHR bank size must be set to 8KB), or the PRG ROM/RAM will be bankswitched as the PPU renders, causing disastrous results. | In these scenarios, however, both CHR bank registers must be set to the same value (or the CHR bank size must be set to 8KB), or the PRG ROM/RAM will be bankswitched as the PPU renders, causing disastrous results. | ||
Revision as of 08:58, 9 January 2019
The generic designation SxROM refers to cartridge boards made by Nintendo that use the Nintendo MMC1 mapper.
Board types
The following SxROM boards are known to exist:
| Board | PRG ROM | PRG RAM | CHR | Comments |
|---|---|---|---|---|
| SAROM | 64 KB | 8 KB | 16 / 32 / 64 KB ROM | NES only |
| SBROM | 64 KB | 16 / 32 / 64 KB ROM | NES only | |
| SCROM | 64 KB | 128 KB ROM | NES only | |
| SC1ROM | 64 KB | 128 KB ROM | Uses 7432 for 28-pin CHR ROM | |
| SEROM | 32 KB | 16 / 32 / 64 KB ROM | ||
| SFROM | 128 / 256 KB | 16 / 32 / 64 KB ROM | ||
| SF1ROM | 256 KB | 64 KB ROM | PRG uses standard 32-pin EPROM pinout | |
| SFEXPROM | 256 KB | 64 KB ROM | Patches PRG at runtime to correct a bad mask ROM run. | |
| SGROM | 128 / 256 KB | 8 KB RAM/ROM | ||
| SHROM | 32 KB | 128 KB ROM | NES only | |
| SH1ROM | 32 KB | 128 KB ROM | Uses 7432 for 28-pin CHR ROM | |
| SIROM | 32 KB | 8 KB | 16 / 32 / 64 KB ROM | Japan Only |
| SJROM | 128 / 256 KB | 8 KB | 16 / 32 / 64 KB ROM | |
| SKROM | 128 / 256 KB | 8 KB | 128 KB ROM | |
| SLROM | 128 / 256 KB | 128 KB ROM | ||
| SL1ROM | 64 / 128 / 256 KB | 128 KB ROM | Uses 7432 for 28-pin CHR ROM | |
| SL2ROM | 128 / 256 KB | 128 KB ROM | CHR uses standard 32-pin EPROM pinout | |
| SL3ROM | 256 KB | 128 KB ROM | Uses 7432 for 28-pin CHR ROM | |
| SLRROM | 128 / 256 KB | 128 KB ROM | Difference from SLROM unknown | |
| SMROM | 256 KB | 8 KB RAM | Japan Only | |
| SNROM | 128 / 256 KB | 8 KB | 8 KB RAM/ROM | |
| SOROM | 128 / 256 KB | 16 KB | 8 KB RAM/ROM | |
| STROM | Not MMC1, actually NROM | |||
| SUROM | 512 KB | 8 KB | 8 KB RAM/ROM | |
| SXROM | 128 / 256 / 512 KB | 32 KB | 8 KB RAM/ROM | Japan Only |
| SZROM | 128 / 256 KB | 16 KB | 16-64 KB ROM | Japan Only |
Solder pad config
Battery data retention
The below pertains to SAROM, SJROM, SKROM, SNROM, SUROM, and SXROM boards only:
- PRG RAM retaining data : 'SL' disconnected, Battery, D1, D2, R1 R2 and R3 present.
- PRG RAM not retaining data : 'SL' connected, leave slots for Battery, D1, D2, R1, R2 and R3 free.
Even if the SOROM boards utilizes a battery, it is connected to only one PRG RAM chip. The first RAM chip will not retain its data, but the second one will.
Higher CHR lines
The SUROM, SOROM, and SXROM boards are extensions of SNROM, which has CHR RAM and PRG RAM. Because CHR RAM doesn't need bankswitching, these boards use the CHR bank select lines to switch different things:
- SNROM uses the upper CHR bank select line coming out of the mapper (CHR A16; bit 4 of bank number) as an additional chip enable for the PRG RAM.[1] All other boards with PRG RAM appear to tie /CE to ground.
- SUROM uses CHR A16 to control the upper address line (PRG A18) of its 512KB PRG ROM.
- SOROM uses a similar method, using the second-highest CHR bank select line to choose between two 8KB PRG RAM chips. Only the RAM chip selected by driving CHR A15 high is battery backed.
- SXROM is a combination of SOROM and SUROM, addressing both 512KB of PRG ROM and 32KB of PRG RAM.
- SZROM retains multiple address lines for CHR ROM banking, but also has 16 KiB of PRG RAM. It uses CHR A16, instead of SOROM's CHR A15, to select between two 8 KiB PRG RAM chips. Similar to SOROM, only the RAM chip selected by driving CHR A16 high is battery backed.
In these scenarios, however, both CHR bank registers must be set to the same value (or the CHR bank size must be set to 8KB), or the PRG ROM/RAM will be bankswitched as the PPU renders, causing disastrous results.
Various notes
- The SEROM, SHROM, and SH1ROM boards, all used for games with 32 KiB PRG such as Dr. Mario, do not connect the PRG ROM's A14 to the MMC1; instead A14 is connected directly to the NES. This means the PRG ROM bank register and the PRG ROM bank mode bits have no effect.[2] SIROM does not seem to share this property, despite having 32 KiB PRG.
- SLxROM boards are functionally identical to SLROM, but with different chip pinouts. Some of them have an additional 74HC32 chip to combine PPU /RD and PPU /A13 into a single enable signal for the CHR ROM chip that has only 28 pins.
- SMROM is functionally identical to SGROM, but features two 128 KB PRG ROM chips instead of one 256 KB. Only a very early MMC1 game in Japan is known to have used this board, and one of very few Nintendo-made boards which combine smaller ROM chips to get a bigger ROM.
- One SNROM game for Famicom uses an 8 KiB CHR ROM instead of CHR RAM: Morita Shogi. The 6264 pinout is nearly identical to the pinout of an 8 KiB mask ROM, except for pins 26 and 27. On the 6264, these are a positive chip enable (CS2) and negative write enable (/WE) respectively; on the mask ROM, they may be additional positive chip enables. Either way, they're high during reads.
- Even boards which different usage of upper CHR lines are all assigned to NES Mapper 1. Emulators can distinguish SOROM and SXROM from SNROM using the new PRG RAM size fields in NES 2.0 or using a PRG hash for legacy iNES ROMs. Therefore, it is recommended that ROM images of SOROM and SXROM games be stored in NES 2.0 format to allow an emulator to distinguish them from SNROM or SUROM.
