Sunsoft 1 pinout: Difference between revisions
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m (switch to using CPU/PRG and PPU/CHR for extra clarity, also boldified deltas) |
m (off-by-one) |
||
Line 3: | Line 3: | ||
.---\/---. | .---\/---. | ||
(n) PPU A12 -> |01 16| -- +5V | (n) PPU A12 -> |01 16| -- +5V | ||
(n) M2 -> |02 15| -> CHR | (n) M2 -> |02 15| -> CHR A14 (r) | ||
(s) /ROMSEL -> |03 14| -> CHR | (s) /ROMSEL -> |03 14| -> CHR A13 (r) | ||
(s) CPU A13 -> |04 13| -> CHR | (s) CPU A13 -> |04 13| -> CHR A12 (r) | ||
(s) CPU A14 -> |05 12| <- CPU RnW (n) | (s) CPU A14 -> |05 12| <- CPU RnW (n) | ||
(s) CPU D5 -> |06 11| <- CPU D0 (s) | (s) CPU D5 -> |06 11| <- CPU D0 (s) |
Revision as of 23:51, 21 August 2012
Sunsoft-1: 16 pin 0.3" PDIP
.---\/---. (n) PPU A12 -> |01 16| -- +5V (n) M2 -> |02 15| -> CHR A14 (r) (s) /ROMSEL -> |03 14| -> CHR A13 (r) (s) CPU A13 -> |04 13| -> CHR A12 (r) (s) CPU A14 -> |05 12| <- CPU RnW (n) (s) CPU D5 -> |06 11| <- CPU D0 (s) (s) CPU D4 -> |07 10| <- CPU D1 (s) GND -- |08 09| <- CPU D2 (s) `--------'
NOTE: D6 is NOT connected, despite what is implied by Mapper 184's writeup. The wiring for Fantasy Zone implies the virtual D6 is treated as though it were connected to +5V always.
Alternative wiring for Fantasy Zone:
.---\/---. (n) CPU A14 -> |01 16| -- +5V (n) M2 -> |02 15| -> PRG A16 (r) (s) /ROMSEL -> |03 14| -> PRG A15 (r) (s) CPU A13 -> |04 13| -> PRG A14 (r) (n) CPU A14 -> |05 12| <- CPU RnW (n) +5V -> |06 11| <- CPU D0 (s) +5V -> |07 10| <- CPU D1 (s) GND -- |08 09| <- CPU D2 (s) `--------'