Sachen 74LS374N pinout: Difference between revisions

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m (that's not what that word means.)
(Provide general and PCB-specific pinouts)
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[[Category:Pinouts]]Sachen “74LS374N”: 20-pin 0.3" DIP or epoxy blob on daughterboard (Canonically [[iNES Mapper 243]])
[[Category:Pinouts]]Sachen fake-marked “74LS374N”: 20-pin 0.3" DIP or epoxy blob on daughterboard).


Most of Sachen's mapper ICs have names that collide with other well-known ICs, presumably as an initial round of misdirection to confuse would-be mass copiers. The 74LS374N is canonically an octal latch (Unlike the [[74377]], the actual '374 would require other support hardware to be used on the NES)
              .---V---.
      R0.0 <- | 01 20 | -- Vcc
CIRAM A10 <- | 02 19 | <- CPU A8
  PPU A11 -> | 03 18 | <- R/W
      R0.1 <- | 04 17 | <- M2
  CPU A14 -> | 05 16 | <- PPU A10
  CPU  A0 -> | 06 15 | <- /ROMSEL
  CPU  D0 <> | 07 14 | <> CPU  D2
  CPU  D1 <> | 08 13 | -> R6.1
      R2.0 <- | 09 12 | -> R6.0
      GND -- | 10 11 | -> R4.0
              '-------'


==Sachen SA-015 PCB ([[INES Mapper 150]])==
               .---V---.
               .---V---.
   PRG A15 <- | 01 20 | -- Vcc
   PRG A15 <- | 01 20 | -- Vcc
  CIRAM A10 <- | 02 19 | <- CPU A8
  CIRAM A10 <- | 02 19 | <- CPU A8
   PPU A11 -> | 03 18 | <- R/W
   PPU A11 -> | 03 18 | <- R/W
        ? ?? | 04 17 | <- M2
  PRG A16 <- | 04 17 | <- M2
   CPU A14 -> | 05 16 | <- PPU A10
   CPU A14 -> | 05 16 | <- PPU A10
   CPU  A0 -> | 06 15 | <- /ROMSEL
   CPU  A0 -> | 06 15 | <- /ROMSEL
   CPU  D0 <> | 07 14 | <> CPU  D2
   CPU  D0 <> | 07 14 | <> CPU  D2
   CPU  D1 <> | 08 13 | -> CHR A16/A14
   CPU  D1 <> | 08 13 | -> CHR A14
  CHR A13 <- | 09 12 | -> CHR A15/A13
      N/C <- | 09 12 | -> CHR A13
       Gnd -- | 10 11 | -> CHR A14/A15
       GND -- | 10 11 | -> CHR A15
               '-------'
               '-------'


Nestopia's source asserts that at least one variant of this mapper can be
==Sachen SA-020A PCB ([[INES Mapper 243]])==
read from.
              .---V---.
 
  PRG A15 <- | 01 20 | -- Vcc
Санчез denoted two different connectivities for the CHR pins. They correspond to the values of the actual hardware, and as exists in current documented dumps (although which is which is not known).
CIRAM A10 <- | 02 19 | <- CPU A8
 
  PPU A11 -> | 03 18 | <- R/W
Reference: Санчез ( http://cah4e3.shedevr.org.ru/%5Blst%5D-sachen-mappers.txt )
  PRG A16 <- | 04 17 | <- M2
  CPU A14 -> | 05 16 | <- PPU A10
  CPU  A0 -> | 06 15 | <- /ROMSEL
  CPU  D0 <> | 07 14 | <> CPU  D2
  CPU  D1 <> | 08 13 | -> CHR A16
  CHR A13 <- | 09 12 | -> CHR A15
      GND -- | 10 11 | -> CHR A14
              '-------'

Revision as of 08:57, 7 December 2019

Sachen fake-marked “74LS374N”: 20-pin 0.3" DIP or epoxy blob on daughterboard). 

             .---V---.
     R0.0 <- | 01 20 | -- Vcc
CIRAM A10 <- | 02 19 | <- CPU A8
  PPU A11 -> | 03 18 | <- R/W
     R0.1 <- | 04 17 | <- M2
  CPU A14 -> | 05 16 | <- PPU A10
  CPU  A0 -> | 06 15 | <- /ROMSEL
  CPU  D0 <> | 07 14 | <> CPU  D2
  CPU  D1 <> | 08 13 | -> R6.1
     R2.0 <- | 09 12 | -> R6.0
      GND -- | 10 11 | -> R4.0
             '-------'

Sachen SA-015 PCB (INES Mapper 150)

             .---V---.
  PRG A15 <- | 01 20 | -- Vcc
CIRAM A10 <- | 02 19 | <- CPU A8
  PPU A11 -> | 03 18 | <- R/W
  PRG A16 <- | 04 17 | <- M2
  CPU A14 -> | 05 16 | <- PPU A10
  CPU  A0 -> | 06 15 | <- /ROMSEL
  CPU  D0 <> | 07 14 | <> CPU  D2
  CPU  D1 <> | 08 13 | -> CHR A14
      N/C <- | 09 12 | -> CHR A13
      GND -- | 10 11 | -> CHR A15
             '-------'

Sachen SA-020A PCB (INES Mapper 243)

             .---V---.
  PRG A15 <- | 01 20 | -- Vcc
CIRAM A10 <- | 02 19 | <- CPU A8
  PPU A11 -> | 03 18 | <- R/W
  PRG A16 <- | 04 17 | <- M2
  CPU A14 -> | 05 16 | <- PPU A10
  CPU  A0 -> | 06 15 | <- /ROMSEL
  CPU  D0 <> | 07 14 | <> CPU  D2
  CPU  D1 <> | 08 13 | -> CHR A16
  CHR A13 <- | 09 12 | -> CHR A15
      GND -- | 10 11 | -> CHR A14
             '-------'
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