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| '''SOROM''' (NES-SOROM and HVC-SOROM) is one of the less common boards within the [[SxROM]] subset. Like other SxROM boards, SOROM uses the [[MMC1|Nintendo MMC1]] ASIC, but because it always uses CHR RAM, it uses a spare CHR address line to select between two PRG RAM chips, letting the program access up to 16 KB of PRG RAM.
| | #REDIRECT [[SxROM]] |
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| == Overview ==
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| * PRG ROM size: 128 or 256 KB (DIP-28/32 Nintendo pinout)
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| * PRG ROM bank size: 16 KB or 32 KB
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| * PRG RAM: 16 KB + battery*
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| * CHR capacity: 8 KB RAM
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| * CHR bank size: 8 KB or 4 KB
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| * Nametable [[mirroring]]: Controlled by mapper
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| * Subject to [[bus conflict]]s: No
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| Though this board utilizes a battery, it is connected to only '''one''' PRG RAM chip. The first RAM chip will not retain its data, but the second one will.
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| Emulators can distinguish SOROM from SNROM using the new PRG RAM size fields in [[NES 2.0]] or using a PRG hash for legacy [[iNES]] ROMs.
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| == Solder pad config ==
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| * Second RAM chip retaining it's data : 'SL' disconnected, Battery, D1, D2 and R2 present.
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| * Both RAM chips not retaining any data : 'SL' connected, leave slots for Battery, D1, D2 and R2 free.
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| == Registers ==
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| The behavior of this board differs from that of a typical MMC1 board in the use of the upper CHR address line:
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| === CHR bank 0 (internal, $A000-$BFFF) ===
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| 4bit0
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| -----
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| xSxxC
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| | +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
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| +---- Select 8 KB PRG RAM bank
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| (0: volatile bank; 1: battery-backed bank)
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| === CHR bank 1 (internal, $C000-$DFFF) ===
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| 4bit0
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| -----
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| xSxxC
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| | +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode)
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| +---- Select 8 KB PRG RAM bank (ignored in 8 KB mode)
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| In 4KB CHR bank mode, the <code>S</code> bits in both CHR bank registers must be set to the same value, or the PRG RAM will be bankswitched as the PPU renders, in a similar fashion as [[MMC3#Hardware|MMC3]]'s scanline counter. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the [[MMC1#Control (internal, $8000-$9FFF)|Control register]].
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