4021

The 4021 is an 8-bit shift register, used in the standard NES and Famicom controllers to latch and output button inputs serially. The 74165 is a similar 8-bit shift register which can be a suitable substitute.

The 4021 stores 8 bits of state in its register when latched, and outputs them one at a time serially when clocked.

4021 Pinout

       .--\/--.
PI-8 ->|01  16|-- Vcc
  Q6 <-|02  15|<- PI-7
  Q8 <-|03  14|<- PI-6
PI-4 ->|04  13|<- PI-5
PI-3 ->|05  12|-> Q7
PI-2 ->|06  11|<- Serial In
PI-1 ->|07  10|<- Clock
 Vss --|08  09|<- Parallel/Serial Control
       '------'

• Vcc - Circuit voltage, usually +5V supply.
• Vss - Negative voltage, usually ground.
• Parallel/Serial Control - When high, the PI inputs are latched into the bits of its register. When low, the Clock input can be activated.
• Clock - When the Parallel/Serial Control is low, and Clock transitions from low to high, each register bit is shifted into to the next higher bit. The value in Q1 is replaced by Serial In, and the value of Q8 is discarded.
• PI-n - Parallel input, replaces bit Qn while Parallel/Serial Control is high.
• Qn - Register state output, the current state of bit 'n'. Q1-Q5 are internal and cannot be read directly.
• Serial In - Replaces Q1 when shifted by a Clock.

The standard controller connects signals from the controller port directly to the 4021:

• +5V -> Vcc
• GND -> Vss, Serial In
• OUT -> Parallel/Serial Control - The last write to $4016:0 controls the latch.
• CLK -> Clock - This is normally high. It goes low when Q8 is read, then returns high to shift the register when the read is finished.
• D0 <- Q8 - Reading the serial output.

By connecting Q8 of one 4021 to the Serial In of another, multiple chips can be chained together into a longer register of 16 bits or more.

74165 Pinout

The 74165 is very similar to the 4021, and aside from pin reordering, is almost compatible except for the inverted latch control:

• /PL is inverted compared to the 4021's 'Parallel/Serial Control'.
• The 74165 numbers its bits 0-7 instead of 1-8.
• Only the last bit is output, instead of the last three, though it also has a second inverted output.

       .--\/--.
 /PL ->|01  16|-- Vcc
  CP ->|02  15|<- /CE
  D4 <-|03  14|<- D3
  D5 <-|04  13|<- D2
  D6 <-|05  12|<- D1
  D7 <-|06  11|<- D0
 /Q7 <-|07  10|<- Ds
 GND --|08  09|-> Q7
       '------'

• Vcc - Circuit voltage, usually +5V supply.
• GND - Ground.
• /PL - When low, the Dn inputs are latched into the register. When high the CP input takes effect. This is inverted, compared to the 4021's Parallel/Serial Control'. One or both of CP and /CE should be high when /PL goes from low to high.
• CP and /CE - Clock input and clock enable. When /CE is low, a low-to-high transition of CP will shift each register bit into the next higher bit. The value in Q0 is replaced by Ds, and the value in Q7 is discarded. These two pins are interchangeable and internally are simply combined as a logical OR.
• Dn - Parallel input, replaces bit Qn while /PL is low. Same as PI-n on 4021 but numbered 0-7 instead of 1-8.
• Q7 - Register state output, the current state of bit 7. Q0-Q6 are internal and cannot be read directly.
• /Q7 - Complementary/inverted Q7.
• Ds - Replaces Q0 when clocked.

Datasheets

• Ti CD4021B
• 74HC165