MMC5 audio
Overview
Nintendo's MMC5 mapper provides extra sound output, consisting of two pulse wave channels and a PCM channel. The pulse wave channels behave almost identically to the native pulse channels in the NES APU.
Pulse 1 ($5000-$5003)
These registers manipulate the MMC5's first pulse wave channel, which functions identically to those found in the NES APU except that it lacks sweep support.
Pulse 2 ($5004-$5007)
These registers manipulate the MMC5's second pulse channel.
PCM Mode/IRQ ($5010)
Write
7 bit 0 ---- ---- Ixxx xxxM | | | +- Mode select (0 = write mode. 1 = read mode.) +--------- PCM IRQ enable (1 = enabled.)
Read
7 bit 0 ---- ---- Ixxx xxxx | +-------- IRQ (0 = No IRQ triggered. 1 = IRQ was triggered.) Reading $5010 acknowledges the IRQ and clears this flag.
Raw PCM ($5011)
This functions similarly to the NES APU's register $4011, except that all 8 bits are used.
Write
7 bit 0 ---- ---- WWWW WWWW |||| |||| ++++-++++- 8-bit PCM data
PCM description
MMC5's DAC is changed either by writing a value to $5011 (in write mode) or reading a value from $8000-BFFF (in read mode). If you try to assign a value of $00, the DAC is not changed; an IRQ is generated instead. This could be used to read stream 8-bit PCM from ROM and terminate at $00.
It uses $8000-$BFFF because the 2A03 DMC uses $C000-$FFFF. However, 2A03 DMC will also wrap to $8000 when it increments from $FFFF. This could be used to allow MMC5 and 2A03 playing the same data at the same time, although it will sound different because of the 8-bit MMC5 PCM format and the 7-bit 2A03 PCM or 1-bit DPCM.
IRQ operation
(pseudocode)
(On DAC write) if(value=0) irqTrip=1 else irqTrip=0 (On $5010 write) irqEnable=value.bit7 (On $5010 read) value.bit7=(irqTrip AND irqEnable) irqTrip=0 Cart IRQ line=(irqTrip AND irqEnable)
Status ($5015, read/write)
This register is analogous to the APU Status register found within the NES at $4015, except that only the bottom 2 bits are used; being for the MMC5's two pulse channels.