MMC5
ExROM
| Company | Nintendo, Koei, others |
| Games | 15 in NesCartDB |
| Complexity | ASIC |
| Boards | EKROM, ELROM, ETROM, EWROM |
| PRG ROM capacity | 1024K |
| PRG ROM window | 8K, 16K, or 32K |
| PRG RAM capacity | 64K |
| PRG RAM window | 8K ($6000-$DFFF), 16K (only $8000-$BFFF at PRG mode 1/2) |
| CHR capacity | 1024K |
| CHR window | 1K, 2K, 4K, or 8K |
| Nametable mirroring | arbitrary, up to 3 source nametables (plus fill mode) |
| Bus conflicts | No |
| IRQ | Yes |
| Audio | Yes |
| iNES mappers | 005 |
The Nintendo MMC5 is a mapper ASIC used in Nintendo's ExROM Game Pak boards. All MMC5 boards are assigned to mapper 5.
Example games:
- Castlevania 3
- Just Breed
- Uncharted Waters
- Romance of the Three Kingdoms II
- Laser Invasion
- Metal Slader Glory
- Uchuu Keibitai SDF
- Shin 4 Nin Uchi Mahjong - Yakuman Tengoku
- Bandit Kings of Ancient China
The first game to use this chip (Nobunaga's Ambition II) was released in February 1990. The date codes on components on early released cartridges show that manufacturing had started at the end of 1989.
Overview
The MMC5 is the most powerful mapper ASIC Nintendo made for the NES and Famicom.
It supports many advanced features, including:
- 4 PRG ROM switching modes
- 4 CHR ROM switching modes
- Up to 64KB of WRAM, mappable not only at $6000-$7FFF but also within $8000-$DFFF
- An 8 bit by 8 bit multiplier with a 16 bit result for performing quick calculations
- A scanline based IRQ counter
- The ability to use different CHR banks for background and 8x16 sprites (allowing 256 unique 8x16 sprite tiles, independent of the background).
- 1024 bytes of on-chip memory, which can be used for 4 different purposes:
- An extra general-use nametable
- Attribute and tile index expansion - address 16384 background tiles at once, and allow each individual 8x8 tile to have its own palette setting
- Vertical split-screen
- Extra RAM for storing program variables
- Three extra sound channels
- Two pulse channels, identical to those in the NES APU (except lacking pitch sweeps).
- An 8-bit RAW PCM channel
- A 'fill mode' nametable, which can be instantly set to contain a specific tile in a specific color (useful for screen transitions)
Banks
The MMC5 provides 4 distinct banking modes for both PRG ROM and CHR ROM.
PRG mode 0
- CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
- CPU $8000-$FFFF: 32 KB switchable PRG ROM bank
PRG mode 1
- CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
- CPU $8000-$BFFF: 16 KB switchable PRG ROM/RAM bank
- CPU $C000-$FFFF: 16 KB switchable PRG ROM bank
PRG mode 2
- CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
- CPU $8000-$BFFF: 16 KB switchable PRG ROM/RAM bank
- CPU $C000-$DFFF: 8 KB switchable PRG ROM/RAM bank
- CPU $E000-$FFFF: 8 KB switchable PRG ROM bank
PRG mode 3
- CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
- CPU $8000-$9FFF: 8 KB switchable PRG ROM/RAM bank
- CPU $A000-$BFFF: 8 KB switchable PRG ROM/RAM bank
- CPU $C000-$DFFF: 8 KB switchable PRG ROM/RAM bank
- CPU $E000-$FFFF: 8 KB switchable PRG ROM bank
CHR mode 0
- PPU $0000-$1FFF: 8 KB switchable CHR bank
CHR mode 1
- PPU $0000-$0FFF: 4 KB switchable CHR bank
- PPU $1000-$1FFF: 4 KB switchable CHR bank
CHR mode 2
- PPU $0000-$07FF: 2 KB switchable CHR bank
- PPU $0800-$0FFF: 2 KB switchable CHR bank
- PPU $1000-$17FF: 2 KB switchable CHR bank
- PPU $1800-$1FFF: 2 KB switchable CHR bank
CHR mode 3
- PPU $0000-$03FF: 1 KB switchable CHR bank
- PPU $0400-$07FF: 1 KB switchable CHR bank
- PPU $0800-$0BFF: 1 KB switchable CHR bank
- PPU $0C00-$0FFF: 1 KB switchable CHR bank
- PPU $1000-$13FF: 1 KB switchable CHR bank
- PPU $1400-$17FF: 1 KB switchable CHR bank
- PPU $1800-$1BFF: 1 KB switchable CHR bank
- PPU $1C00-$1FFF: 1 KB switchable CHR bank
Registers
Sound
For details on sound operation, see MMC5 audio
Configuration
PRG mode ($5100)
7 bit 0
---- ----
xxxx xxPP
||
++- Select PRG banking mode
- 0 - One 32KB bank
- 1 - Two 16KB banks
- 2 - One 16KB bank ($8000-$BFFF) and two 8KB banks ($C000-$DFFF and $E000-$FFFF)
- 3 - Four 8KB banks
Castlevania III uses mode 2, which is similar to VRC6 PRG banking. All other games use mode 3. The Koei games never write to this register, apparently relying on the MMC5 defaulting to mode 3 at power on.
CHR mode ($5101)
7 bit 0
---- ----
xxxx xxCC
||
++- Select CHR banking mode
- 0 - 8KB CHR pages
- 1 - 4KB CHR pages
- 2 - 2KB CHR pages
- 3 - 1KB CHR pages
Metal Slader Glory uses 4KB CHR pages. All other games use 1KB pages.
PRG RAM Protect 1 ($5102)
7 bit 0
---- ----
xxxx xxWW
||
++- RAM protect 1
In order to enable writing to PRG RAM, this must be set to binary '10' (e.g. $02).
PRG RAM Protect 2 ($5103)
7 bit 0
---- ----
xxxx xxWW
||
++- RAM protect 2
In order to enable writing to PRG RAM, this must be set to binary '01' (e.g. $01).
Extended RAM mode ($5104)
7 bit 0
---- ----
xxxx xxXX
||
++- Specify extended RAM usage
- 0 - Use as extra nametable (possibly for split mode)
- 1 - Use as extended attribute data (can also be used as extended nametable)
- 2 - Use as ordinary RAM
- 3 - Use as ordinary RAM, write protected
Nametable mapping ($5105)
7 bit 0 ---- ---- DDCC BBAA |||| |||| |||| ||++- Select nametable at PPU $2000-$23FF |||| ++--- Select nametable at PPU $2400-$27FF ||++------ Select nametable at PPU $2800-$2BFF ++-------- Select nametable at PPU $2C00-$2FFF
Nametable values:
- 0 - On-board VRAM page 0
- 1 - On-board VRAM page 1
- 2 - Internal Expansion RAM, only if the Extended RAM mode allows it ($5104 is 00/01); otherwise, the nametable will read as all zeros,
- 3 - Fill-mode data
Mirroring examples:
| Mode | Value | NTD | NTC | NTB | NTA |
|---|---|---|---|---|---|
| Horizontal | $50 | %01 | %01 | %00 | %00 |
| Vertical | $44 | %01 | %00 | %01 | %00 |
| 1-Screen CIRAM 0 | $00 | %00 | %00 | %00 | %00 |
| 1-Screen CIRAM 1 | $55 | %01 | %01 | %01 | %01 |
| 1-Screen ExRAM | $AA | %10 | %10 | %10 | %10 |
| 1-Screen Fill-mode | $FF | %11 | %11 | %11 | %11 |
| Diagonal | $14 | %00 | %01 | %01 | %00 |
| L-Shaped | $54 | %01 | %01 | %01 | %00 |
| 3-Screen Horizontal | $A4 | %10 | %10 | %01 | %00 |
| 3-Screen Vertical | $98 | %10 | %01 | %10 | %00 |
| 3-Screen Diagonal | $94 | %10 | %01 | %01 | %00 |
| Pseudo 4-Screen | $E4 | %11 | %10 | %01 | %00 |
Fill-mode tile ($5106)
All eight bits specify the tile number to use for fill-mode nametable
Fill-mode color ($5107)
7 bit 0
---- ----
xxxx xxAA
||
++- Specify attribute bits to use for fill-mode nametable
PRG Bankswitching
PRG RAM bank ($5113)
7 bit 0
---- ----
xxxx xCBB
|||
|++- Select 8KB PRG RAM bank at $6000-$7FFF
+--- Select PRG RAM chip
The MMC5 supports 2 PRG RAM chips, each up to 32KB in length. Either or both may be battery-backed; 11 of the 15 MMC5 games include a battery. The following configurations of WRAM are known to exist in ExROM games:
- 0KB: No chips
- 8KB: 1x 8KB chip
- 16KB: 2x 8KB chip
- 32KB: 1x 32KB chip
In the original .NES format, byte 8 of the file's header should indicate how many pages are present, but ROM images in the wild that use this mapper may not have byte 8 set correctly, nor do emulators necessarily honor this number. Byte 10 of the NES 2.0 header should be reliable.
No ExROM game is known to write PRG RAM with one bank value and then attempt to read back the same data with a different bank value. So lacking better information, mirroring can be ignored, 64KB of WRAM could be emulated at all times, and $5113 can be treated as a simple page offset into that 64KB. Emulating 32KB won't work, even if no games used more than that; because 16KB games will expect to see their two distinct pages by toggling bit 2, not bit 0.
Uncharted Waters requires PRG-RAM banking.
PRG bank 0 ($5114)
7 bit 0 ---- ---- RBBB BBBB |||| |||| |+++-++++- Bank number +--------- RAM/ROM toggle (0: RAM; 1: ROM)
- Mode 0 - Ignored
- Mode 1 - Ignored
- Mode 2 - Ignored
- Mode 3 - Select an 8KB PRG bank at $8000-$9FFF
When selecting a RAM bank, treat bank bits as indicated for the PRG RAM bank register at $5113.
Bandit Kings of Ancient China maps PRG-RAM to the CPU $8000+ area and expects to be able to write to it through there. Failure to emulate this causes corruption when the background is restored on the world map.
PRG bank 1 ($5115)
7 bit 0 ---- ---- RBBB BBBB |||| |||| |+++-++++- Bank number +--------- RAM/ROM toggle (0: RAM; 1: ROM)
- Mode 0 - Ignored
- Mode 1 - Select a 16KB PRG bank at $8000-$BFFF (ignore bottom bit)
- Mode 2 - Select a 16KB PRG bank at $8000-$BFFF (ignore bottom bit)
- Mode 3 - Select an 8KB PRG bank at $A000-$BFFF
When selecting a RAM bank, treat bank bits as indicated for the PRG RAM bank register at $5113.
PRG bank 2 ($5116)
7 bit 0 ---- ---- RBBB BBBB |||| |||| |+++-++++- Bank number +--------- RAM/ROM toggle (0: RAM; 1: ROM)
- Mode 0 - Ignored
- Mode 1 - Ignored
- Mode 2 - Select an 8KB PRG bank at $C000-$DFFF
- Mode 3 - Select an 8KB PRG bank at $C000-$DFFF
When selecting a RAM bank, treat bank bits as indicated for the PRG RAM bank register at $5113.
PRG ROM bank 3 ($5117)
7 bit 0 ---- ---- xBBB BBBB ||| |||| +++-++++- PRG ROM bank number
- Mode 0 - Select a 32KB PRG ROM bank at $8000-$FFFF (ignore bottom 2 bits)
- Mode 1 - Select a 16KB PRG ROM bank at $C000-$FFFF (ignore bottom bit)
- Mode 2 - Select an 8KB PRG ROM bank at $E000-$FFFF
- Mode 3 - Select an 8KB PRG ROM bank at $E000-$FFFF
Games seem to expect $5117 to be $FF at power on. All games have their reset vector in the last bank of PRG ROM, and the vector points to an address greater than or equal to $E000.
CHR Bankswitching ($5120-$5130)
When using 8x8 sprites, only registers $5120-$5127 are used. Registers $5128-$512B are completely ignored.
When using 8x16 sprites, registers $5120-$5127 specify banks for sprites, registers $5128-$512B apply to background tiles, and the last set of registers written to (either $5120-$5127 or $5128-$512B) will be used for I/O via PPUDATA ($2007). [1] [2]
Bandit Kings of Ancient China and Uchuu Keibitai SDF have non-pattern data stored in CHR ROM, read out via $2007.
It is not currently known how the MMC5 detects the sprite size being used by the PPU.
CHR selects 0…11
| PPU memory affected for each mode (see #CHR mode ($5101)) | ||||
|---|---|---|---|---|
| Write to CPU address | 1 KiB | 2 KiB | 4 KiB | 8 KiB |
| $5120 | $0000-$03FF | none | none | none |
| $5121 | $0400-$07FF | $0000-$07FF | none | none |
| $5122 | $0800-$0BFF | none | none | none |
| $5123 | $0C00-$0FFF | $0800-$0FFF | $0000-$0FFF | none |
| $5124 | $1000-$13FF | none | none | none |
| $5125 | $1400-$17FF | $1000-$17FF | none | none |
| $5126 | $1800-$1BFF | none | none | none |
| $5127 | $1C00-$1FFF | $1800-$1FFF | $1000-$1FFF | $0000-$1FFF |
| $5128 | $0000-$03FF and $1000-$13FF | none | none | none |
| $5129 | $0400-$07FF and $1400-$17FF | $0000-$07FF and $1000-$17FF | none | none |
| $512A | $0800-$0BFF and $1800-$1BFF | none | none | none |
| $512B | $0C00-$0FFF and $1C00-$1FFF | $0800-$0FFF and $1800-$1FFF | $0000-$0FFF and $1000-$1FFF | $0000-$1FFF |
Upper CHR Bank bits ($5130)
7 bit 0
---- ----
xxxx xxBB
||
++- Upper bits for subsequent CHR bank writes
When the MMC5 is using 2KB/1KB CHR banks, only 512KB/256KB of CHR ROM can be selected using the previous registers. To access all 1024KB in those modes, first write the upper bit(s) to register $5130 and then write the lower bits to $5120-$512B. When the Extended RAM mode is set to 1, this selects which 256KB of CHR ROM is to be used for all background tiles on the screen.
The only ExROM game with CHR ROM larger than 256KB is Metal Slader Glory, which uses 4KB CHR banks and does not use extended attributes. In other words, no official game relies on this register, and most don't even initialize it.
Other Registers
Vertical Split Mode ($5200)
7 bit 0 ---- ---- ESxW WWWW || | |||| || +-++++- Specify vertical split start/stop tile |+-------- Specify vertical split screen side (0:left; 1:right) +--------- Enable vertical split mode
When vertical split mode is enabled, all VRAM fetches corresponding to the appropriate screen region will be redirected to Extended RAM (as long as its mode is set to 0 or 1).
Uchuu Keibitai SDF is the only known game to use split screen mode (during the intro, where it shows ship stats).
Operation Notes
34 BG tiles are fetched per scanline. MMC5 performs the split by watching which BG tile is being fetched, and if it is within the split region, replacing the normal NT data with the split screen data according to the absolute screen position of the tile (i.e., ignoring the coarse horizontal and vertical scroll output as part of the VRAM address for the fetch). Since it operates on a per-tile basis... fine horizontal scrolling "carries into" the split region. Setting the horizontal scroll to 1-7 will result in the split being moved to the left 1-7 pixels, however when you scroll to 8, the split will "snap" back to its normal position.
Left Split:
- Tiles 0 to T-1 are the split.
- Tiles T and on are rendered normally.
Right Split:
- Tiles 0 to T-1 are rendered normally.
- Tiles T and on are the split.
There is no coarse horizontal scrolling of any kind for the split. Right-side splits will always show the right-hand side of the nametable, and left-hand splits will always show the left-hand side of the nametable. Coarse horizontal scrolling can still be used for the non-split region.
ExRAM is always used as the nametable in split screen mode.
Vertical scrolling for the split operates like normal vertical scrolling. 0-239 are valid scroll values, whereas 240-255 will display Attribute table data as NT data for the first few scanlines. The split nametable will wrap so that the top of the nametable will appear below as you scroll (just as if vertical mirroring were employed).
$5202 selects (yet another) CHR page to use for the BG. This page is used for the split region only.
Vertical Split Scroll ($5201)
All eight bits specify the vertical scroll value to use in split region
MMC5 boards wired in "CL" mode may only use vertical scroll values whose bottom 3 bits match the Nes PPU's fine vertical scroll value. In "SL" mode, any values can be used.
Horizontal scrolling is not allowed within the split region.
Vertical Split Bank ($5202)
All eight bits select a 4 KB CHR bank at $0000-$0FFF and $1000-$1FFF while rendering the split region.
IRQ Counter ($5203)
All eight bits specify the scanline number to generate IRQ at
IRQ Status ($5204, read/write)
Write
7 bit 0 ---- ---- Exxx xxxx | +--------- IRQ Enable flag (1=IRQs enabled)
Read
7 bit 0 ---- ---- SVxx xxxx || |+-------- "In Frame" signal +--------- IRQ Pending flag
When set, the "In Frame" signal specifies that the PPU is currently rendering a scanline. It also plays a role in how IRQs are generated.
The IRQ Pending flag may be raised even if IRQs are disabled.
Any time this register is read, the IRQ Pending flag is cleared (acknowledging the IRQ).
For details, see IRQ counter operation.
Multiplier ($5205, read/write)
Writes specify the eight-bit multiplicand; reads return the lower eight bits of the product
Multiplier ($5206, read/write)
Writes specify the eight-bit multiplier; reads return the upper eight bits of the product
Expansion RAM ($5C00-$5FFF, read/write)
- Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
- Mode 2 - Readable and writable
- Mode 3 - Read-only
In Mode 1, nametable fetches are processed normally, and can come from CIRAM nametables, fill mode, or even Expansion RAM, but attribute fetches are replaced by data from Expansion RAM.
Each byte of Expansion RAM is used to enhance the tile at the corresponding address in every nametable (so the extended attributes are 1-screen mirrored):
7 bit 0 ---- ---- AACC CCCC |||| |||| ||++-++++- Select 4 KB CHR bank to use with specified tile ++-------- Select palette to use with specified tile
The pattern fetches ignore the standard CHR banking bits, and instead use the top two bits of $5130 and the bottom 6 bits from Expansion RAM to choose a 4KB bank to select the tile from.
Just Breed, Yakuman Tengoku, and the Koei games use extended attributes continuously.
IRQ Counter Operation
The MMC5 has an 8-bit incrementing IRQ counter that watches the PPU as it renders, and counts each passing scanline. When the counter reaches the desired IRQ scanline (specified by the $5203 register), it signals an IRQ. It also uses an In Frame signal which can be read from $5204.6 in conjunction with the 8-bit counter. Games can use this signal as an indication of whether or not the PPU is currently in rendering time.
The game has no direct access to the internal IRQ counter.
How the MMC5 actually detects scanlines is still unknown. The best evidence now is that it watches for the two dummy nametable reads which occur at the end of each scanline, see [3]. It appears that all 240 rendered scanlines as well as the pre-render scanline are all detected by the MMC5. It also appears that scanlines are detected near their end (or near the start of the next scanline). When a game sets the desired IRQ scanline to $04, the IRQ will occur near the start of the 5th rendered scanline.
When the MMC5 detects a scanline, the following events occur:
- if the In Frame signal is clear, set it, reset the IRQ counter to 0, and clear the IRQ Pending flag
- otherwise, increment the IRQ counter. If it now equals the IRQ scanline ($5203), raise IRQ Pending flag
Note the above logic makes it impossible for an IRQ to occur when $5203 is set to $00
The In Frame signal is cleared as soon as the MMC5 no longer detects PPU rendering. This happens at the end of the last rendered scanline, and whenever the PPU is switched off (Sprite and BG rendering disabled).
Note that there are side-effects to switching off the PPU mid frame. Clearing the In Frame signal effectively resets the IRQ counter as can be seen in the logic given above. Therefore, if the PPU is switched back on in the frame, the IRQ counter will begin counting from $00 again.
The IRQ Pending flag is raised when the desired scanline is reached regardless of whether or not IRQs are enabled. $5204.7 can still be read as set even when IRQ Enable flag is clear. However, an actual IRQ is only sent to the CPU if both the IRQ Enable flag and IRQ Pending flag are raised.
Hardware
The MMC5 exists in a 100-pin TQFP package, see MMC5 pinout for details.
MMC5 cartridge PCBs can be configured to different modes, see ExROM for details.
At least two different versions of the MMC5 are known to exist: MMC5, and MMC5B. Their differences are unknown.
