INES Mapper 034

iNES Mapper 034 denotes the unrelated NINA-001/NINA-002 and BNROM circuit boards. The NES 2.0 Submapper differentiates the two:

• Submapper 1 denotes the NINA-001/NINA-002 circuit board,
• Submapper 2 denotes the BNROM circuit board.

In the absence of valid submapper information, mapper 34 .NES files should be considered BNROM when the CHR-ROM size is 0-8 KiB, and NINA-001/NINA-002 when the CHR-ROM size is above 8 KiB.

NINA-001/NINA-002

NINA-001

Company	American Video Entertainment
Games	1 in NesCartDB
Complexity	Discrete logic
Boards	NINA-001
PRG ROM capacity	64K
PRG ROM window	32K
PRG RAM capacity	8K
PRG RAM window	n/a
CHR capacity	64K
CHR window	4K
Nametable mirroring	Fixed H
Bus conflicts	No
IRQ	No
Audio	No
iNES mappers	034

NESCartDB

NINA-001

NINA-002

The NINA-001 PCB supports 64 KiB of PRG-ROM capacity and uses a microcontroller to disable the CIC. The NINA-002 PCB increases PRG-ROM capacity to 128 KiB and uses a stun circuit to disable the CIC.

Banks

• CPU $6000-$7FFF: 8 KiB of unbanked PRG-RAM.
• CPU $8000-$FFFF: 32 KiB window into 64 KiB (NINA-001)/128 KiB (NINA-002) of PRG-ROM
• PPU $0000-$0FFF: 4 KiB window into 64 KiB of CHR-ROM
• PPU $1000-$1FFF: 4 KiB window into 64 KiB of CHR-ROM
• Nametable arrangement: Fixed vertical arrangement ("Horizontal mirroring")

Registers

The registers overlapping PRG-RAM at the same addresses mean that reading the register's address returns the last value written to the PRG-RAM, which is also the last value written to the register.

PRG Bank Select ($7FFD, write)

D~[.... ..BA] A~[0111 1111 1111 1101]
          ++- PRG A16..A15 (32 KiB bank)

The power-on value is undefined; games should have a reset vector and handler in all PRG-ROM banks.

CHR Bank Select 0 ($7FFE, write)

D~[.... DCBA] A~[0111 1111 1111 1110]
        ++++- CHR A15..A12 (4 KiB bank) at PPU $0000

CHR Bank Select 1 ($7FFF, write)

D~[.... DCBA] A~[0111 1111 1111 1111]
        ++++- CHR A15..A12 (4 KiB bank) at PPU $1000

BNROM

BNROM

Company	Irem, Nintendo
Games	2 in NesCartDB
Complexity	Discrete logic
Boards	I-IM, BNROM
PRG ROM capacity	128K
PRG ROM window	32K
PRG RAM capacity	None
CHR capacity	8K
CHR window	n/a
Nametable mirroring	Fixed H or V, controlled by solder pads
Bus conflicts	Yes
IRQ	No
Audio	No
iNES mappers	034, 241, 177

NESCartDB

BNROM

Banks

• CPU $8000-$FFFF: 32 KiB window into 128 KiB of PRG-ROM
• PPU $0000-$1FFF: 8 KiB of unbanked CHR-RAM/-ROM
• Nametable arrangement: Fixed; solder pad selects between Horizontal and Vertical

Register: Bank Select ($8000-$FFFF, write)

D~[.... ..BA] A~[1... .... .... ....]
          ++- PRG A16..A15 (32 KiB bank)

• The power-on value is undefined; games should have a reset vector and handler in all PRG-ROM banks.
• The original BNROM board is always subject to AND-type bus conflicts: the effective value is the value being written bitwise-AND'd with the PRG-ROM content at the address being written to.

See also

iNES Mapper 241 is a variation of BxROM with 8 KiB PRG-RAM at CPU $6000-$7FFF, avoids bus conflicts, and optionally supports an LPC speech chip.