New Features

V.R. Technology's NES-on-a-chip consoles feature enhance the original NES/Famicom in several aspects.

VT02+ Features

OneBus mode: PRG and CHR data come from the same address space. The cartridge connector's PPU Address lines are repurposed as higher-order CPU Address lines.
Integrated MMC3-compatible bankswitching by the console, active when in OneBus mode.
Ability to use NTRAM as CHR-RAM.
Choice of A12 and HBLANK as a source for clocking the scanline interrupt.
Automatic X/Y light gun position determination.
Integrated RS232 interface.
Direct NTSC/PAL and 50/60 Hz identification.
Automatic per-attribute-tile background and per-sprite sprite bankswitching.
DMA can be used to transfer data to PPU memory (via $2007) in addition to the normal transferring of data to OAM memory (via $2004).
A second APU doubling the number of sound channels.
Raw PCM output using full eight bits of resolution.
DMA-driven raw PCM output.
Data for DMA-driven DPCM/PCM output can be placed anywhere in CPU address space, not just within the $C000-$FFFF range.

VT03+ Features

Sprites can be 16 pixels wide.
Graphics can be in four-bits-per-pixel format in addition to the regular two-bits-per-pixel format.
Enhanced color palette with twelve bits per color.

VT16+ Features

Internal CPU RAM is 4 KiB rather than just 2 KiB.
The CPU can be set to run at the same speed (5.37 MHz) as the PPU.
The CPU can be set to retrieve interrupt vectors from RAM ($0FFx) rather than ROM ($FFFx).
DMA-driven DPCM/PCM output can be set to use its own banking registers independent of normal PRG banking.
Hardware random number generator.

In this description, features are assigned to the earliest console type for which a datasheet is publicly available. The publicly-available datasheets are for the VT01, VT02, VT03, VT16 and VT18. Therefore, a feature described as VT16+ may have been available earlier on VT04 to VT15 consoles.

Memory Map

CPU Memory Map

CPU $0000-$07FF: 2 KiB of internal RAM
CPU $0800-$0FFF: VT16+: VT01-VT03: Mirror of CPU $0000-$07FF, VT16+: Further 2 KiB of internal RAM
CPU $1000-$1FFF: Mirror of CPU $0000-$0FFF
CPU $2000-$2007: Famicom-compatible PPU registers
CPU $2010-$201F: New PPU registers
CPU $4000-$401F: Famicom-compatible APU, DMA and I/O registers
CPU $4020-$403F: New APU, DMA and I/O registers
CPU $4100-$41FF: New miscellaneous registers
CPU $6000-$7FFF: Optional WRAM, if present on cartridge
CPU $8000-$FFFF (write): When forwarding is enabled (see register $410B): MMC3-compatible registers that are forwarded to $4101-$4108)
CPU $8000-$FFFF (read): Four 8 KiB PRG-ROM banks. See the section "PRG ROM Bankswitching" for details.

PPU Memory Map

PPU $0000-$1FFF: CHR-ROM/CHR-RAM: VT03+ in 4 bits-per-pixel modes: bits 0 and 1 of each pixel
PPU $2000-$2FFF: NTRAM (2 KiB, selectable mirroring)
PPU $3F00-$3F7F: CGRAM, lower six bits of each color
PPU $3F80-$3FFF: VT03: CGRAM, upper six bits of each color (only used if $2010 bit 7=1) 
PPU $4000-$5FFF: VT03+ in 4 bits-per-pixel modes: CHR-ROM/CHR-RAM bits 2 and 3 of each pixel

PRG-ROM Bankswitching

The bankswitching scheme is based on, and indeed backwards-compatible to, the Nintendo MMC3's. The CPU address range is divided into four 8 KiB banks. For each of these four 8 KiB banks, the bank number is made up of four components:

an Inner Bank that resembles the MMC3's bank registers,
a Middle Bank that can replace zero to eight bits of the lower bank number,
an Outer Bank that extend the address range up to 32 MiB.
a Relative Bank that adds a fixed value to the previous three components (VT16+ only).

The final 8 KiB PRG-ROM bank number therefore is:

BankNumber := ((InnerBank &InnerBankMask) | (MiddleBank &~InnerBankMask) | (OuterBank <<8)) +RelativeBank;

Inner Bank number

The lower bits bits of the 8 KiB PRG-ROM bank number, constituting the Inner Bank number, are normally the only ones that are manipulated by individual games. By default, they resemble the MMC3's original bank registers; accordingly, two of the four banks are fixed. By setting bit 6 in register $410B (PQ2EN), the $C000-$DFFF bank may be turned into a selectable bank as well.

CPU $8000-$9FFF: Selected by register $4107 (PQ0), akin to MMC3 register 6.
CPU $A000-$BFFF: Selected by register $4108 (PQ1), akin to MMC3 register 7.
CPU $C000-$DFFF: If $410B bit 6 (PQ2EN)=0: Fixed to $FE, or second-to-last bank (within the Middle/Outer Bank), as on the MMC3.
                 If $410B bit 6 (PQ2EN)=1: Selected by register $4109 (PQ2), an enhancement over the MMC3.
CPU $E000-$FFFF: Fixed to $FF, or last bank (within the Middle/Outer Bank), as on the MMC3.

If $4105 bit 6 (COMR6) is 1, then the sources for the $8000-$9FFF/$A000-$BFFF banks are swapped with the $C000-$DFFF/$E000-$FFFF banks', just as on the MMC3.

Middle Bank mask and number

The Middle Bank is normally only used on multicarts. It allows masking off and replacing bits of the Inner Bank number, so that several games may be put into one Outer Bank. Bits 0-2 of register $410B (PS) select the AND mask that is applied to the Inner Bank number. Only the bits that have been masked off that way are then replaced with the respective bits from register $410A (PQ3):

$410B     Inner Bank  Middle Bank Effective
bits 0-2  AND Mask    AND Mask    Inner Bank Size
--------  ----------  --------    ---------------
0         3F          C0          512 KiB
1         1F          E0          256 KiB
2         0F          F0          128 KiB
3         07          F8          64 KiB
4         03          FC          32 KiB
5         01          FE          16 KiB
6         00          FF          8 KiB
7         FF          00          2048 KiB

Outer Bank Number

The Outer Bank number is used mostly by multicarts, but also by very large games for which the maximum Inner Bank size of 2 MiB is insufficient. On the VT02 and VT03, bits 4-7 of register $4100 simply select the 2 MiB Outer Bank number. On the VT16+, if register $411C bit 5 (EXT2421EN) is set, each of the four 8 KiB banks in the CPU $8000-$FFFF address range can be selected individually.

VT02, VT03; VT16+ with $411C bit 5 (EXT2421)=0:

CPU $8000-$FFFF: Selected by register $4100 bits 4-7 (PQ7).

VT16+ with $411C bit 6 (EXT2421)=1:

CPU $8000-$9FFF: Selected by register $4110 bits 0-3 (PQ4).
CPU $A000-$BFFF: Selected by register $4110 bits 4-7 (PQ5).
CPU $C000-$DFFF: If $410B bit 6 (PQ2EN)=0: Selected by $4100 bits 4-7 (PQ7), as on VT02/VT03.
                 If $410B bit 6 (PQ2EN)=1: Selected by $4111 bits 0-3 (PQ6).
CPU $E000-$FFFF: Selected by $4100 bits 4-7 (PQ7), as on VT02/VT03.

If $4105 bit 6 (COMR6) is 1, then the sources for the $8000-$9FFF/$A000-$BFFF banks are swapped with the $C000-$DFFF/$E000-$FFFF banks', as was the case with the Inner Bank number.

Relative Bank Number

The Relative Bank only exists on the VT16 and later consoles. While Inner, Middle and Outer Bank numbers are combined with AND and OR operations, the Relative Bank is simply added, yielding much greater flexibility. The Relative Bank Number is defined by registers $4127 (bits 0-7) and $4128 (bits 0-2), yielding 11 bits. Because the Relative Bank number has only eleven rather than the twelve bits of the combined Inner, Middle and Outer Bank numbers, it is guaranteed that final bank number does not overflow within the defined address space.

CHR-ROM Layout and Bankswitching

The layout of CHR-ROM, and by consequence the meaning of the CHR bank registers, is dependent on the current video mode. The concept of a video mode is rarely applied to the original NES/Famicom, as it would be considered to only have a single one. Things are more complex on the VTxx series: the VT02 has two, the VT03 has four, and the VT16+ have six video modes defined by the number of bits per pixel, whether Address Extension is used, and whether the Video Data Bus has eight or sixteen bits.

Bits per pixel	Address Extension	Video Data Bus Width
Bits per pixel	Address Extension	8 bit	16 bit
2	off	VT02	-
2	on	VT02	-
4	off	VT03	VT16+
4	on	VT03	VT16+

Bits per pixel

The number of bits per pixel is selected separately for background and sprites. For sprites in four bits per pixel mode, it can further be selected whether the second pair of bits is to be used to form a four-bit color number, or whether they are used to increase the number of horizontal pixels per sprite from eight to sixteen. For the background, the number of bits per pixel is selected by register $2010 bit 1 (BK16EN), for sprites by register $2010 bit 2 (SP16EN), with a cleared bit selecting two bits per pixel, and a set bit selecting four bits per pixel.

On the VT03, the choice between sixteen colors per sprite --- register $2010 bit 0 (PIX16EN) cleared --- and sixteen pixels per sprite --- register $2010 bit 0 (PIX16EN) set --- applies to all sprites. On the VT16+, the same applies if register $2010 bit 5 (SPOPEN) is cleared; if register $2010 bit 2 (SP16EN) and bit 5 (SPOPEN) are both set, the choice can be made for each sprite individually by clearing (sixteen colors) or setting (sixteen pixels) bit 4 of byte 2 of that sprite's OAM data.

User:NewRisingSun/VTxx

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