Talk:CPU power up state
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Parts of the APU which appear to be affected by reset (determined by tracing the reset signal throughout the chip):
- Square channel volume/envelope timer (not the reload value at $4000/$4004 bits 0-3) and counter (the actual volume output)
- Noise channel volume/envelope timer (not the reload value at $4008 bits 0-3) and counter (the actual volume output)
- Square channel frequency counter, including the 3 duty cycle bits
- Triangle channel frequency counter
- Noise channel frequency counter, sort of - it forces the LFSR input to 0, so a very short reset pulse might only partially clear it
- DPCM channel frequency counter, sort of - it forces the LFSR input to 0, so a very short reset pulse might only partially clear it
- Noise channel frequency ($400E bits 0-3)
- Square channel sweep counter
- All 4 length counters
- All 5 channel enables ($4015)
- Triangle channel linear counter (not the reload value at $4008)
- Triangle channel Position
- DPCM channel Sample Length counter (not the reload value)
- DPCM channel Position ($4011)
- DPCM channel Sample Buffer and Bit Counter
- DPCM channel Sample Address counter (not the reload value)
- DPCM channel state machine
- Sprite DMA address counter and state machine
- Part of the Frame Counter (notably, not the two writable bits of $4017)
- Debug register $401A bit 7
--Quietust 16:40, 8 June 2011 (UTC)
