Talk:APU DMC

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Revision as of 05:00, 23 January 2011 by Quietust (talk | contribs) (Created page with 'Similarly to the noise channel, the DPCM channel's frequency counter [http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/ on the die] is a '''9-bit linear …')
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Similarly to the noise channel, the DPCM channel's frequency counter on the die is a 9-bit linear feedback shift register (with taps at the 5th and 9th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '100000000', the cycle counts (for NTSC) match exactly. --Quietust 05:00, 23 January 2011 (UTC)

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