User contributions for Ben Boldt
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8 May 2021
- 04:1004:10, 8 May 2021 diff hist −97 Famicom Network System →RF5A18 CPU2 / Modem Controller: Reverting incorrect change I introduced on May 3, 2021. Pins 65&66 are bidirectional using $40D4.
7 May 2021
- 03:1703:17, 7 May 2021 diff hist +259 Famicom Network System →CPU2 Known Registers: Added $4112.2: UART Tx Idle. Clarified that $4112.1 indicates the Tx buffer is ready.
- 01:4501:45, 7 May 2021 diff hist −5 m Famicom Network System Cleanup
6 May 2021
- 02:2102:21, 6 May 2021 diff hist +60 Famicom Network System →CPU2 Known Registers: Added $4112.5 framing error, thanks to lidnariq.
- 01:2801:28, 6 May 2021 diff hist +910 Famicom Network System →CPU2 Known Registers: Confirmed some things for UART Rx, found parity error flag for Rx.
5 May 2021
- 23:4923:49, 5 May 2021 diff hist +208 m Famicom Network System →CPU2 Known Registers: Clarify that the UART Rx does appear to trigger an IRQ somehow, will try to confirm that with a bench test somehow.
- 16:1416:14, 5 May 2021 diff hist +533 Famicom Network System →CPU2 Known Registers: Improved built-in ROM observations of register $4111.
- 01:4701:47, 5 May 2021 diff hist +173 Famicom Network System →Known Registers: Added notes to $40D5 about reading it in real-time.
- 01:3301:33, 5 May 2021 diff hist +96 Famicom Network System →CPU2 Known Registers: Found pin 33 (MSM6827L /INT) and pin 73 (Tone Rx DV) IRQ enables on the RF5A18 chip, register $412F
- 00:4100:41, 5 May 2021 diff hist −63 Famicom Network System →CPU2 Known Registers: Removed $4113.4 write after not being able to reproduce it.
- 00:3500:35, 5 May 2021 diff hist +302 Famicom Network System →CPU2 Known Registers: Added even/odd parity for UART in $4111.
4 May 2021
- 23:4523:45, 4 May 2021 diff hist +474 Famicom Network System →CPU2 Known Registers: Added more UART findings.
- 13:3813:38, 4 May 2021 diff hist +63 m Famicom Network System →CPU2 Known Registers: Cleanup.
- 04:3604:36, 4 May 2021 diff hist +2 m Famicom Network System →CPU2 Known Registers: Fixed error where I put $4112.2 as read instead of write.
- 02:1002:10, 4 May 2021 diff hist +935 Famicom Network System →CPU2 Known Registers: Added some control register bits that affect pin 90 (MSM6827L TXD)
- 01:1501:15, 4 May 2021 diff hist 0 Famicom Network System →RF5A18 CPU2 / Modem Controller: Corrected RF5A18 pins 38, 39 are outputs only, pins 65, 66 are input only (none of those appear to behave bidirectional).
- 00:1900:19, 4 May 2021 diff hist +57 Famicom Network System →CPU2 Known Registers: Note that Pin 32 is a push-pull output when set as output mode in $4120.6
- 00:0800:08, 4 May 2021 diff hist +579 Famicom Network System Added info for $40D5.4 frequency depending on value written to $4114 bits 1 and 0.
2 May 2021
- 02:0402:04, 2 May 2021 diff hist +383 Famicom Network System →CPU2 Known Registers: Added details for $4120/$4121 input/output modes for pin 32.
- 01:3001:30, 2 May 2021 diff hist −43 Famicom Network System Updated push-pull vs. open drain configuration of Exp P3-17,18,19 via Famicom register $40D4.
- 00:1500:15, 2 May 2021 diff hist −68 m Famicom Network System →Known Registers: cleanup
1 May 2021
- 23:3023:30, 1 May 2021 diff hist +313 Famicom Network System Found more connections with register $40D6, depending on CPU2 registers $4112 and $4113.
- 01:4501:45, 1 May 2021 diff hist +1,492 Famicom Network System Added /IRQ pin to CPU2, removed +IRQ (can't replicate that), added info about $412F.5 IRQ
27 April 2021
- 15:1415:14, 27 April 2021 diff hist +432 Famicom Network System →CPU2 Known Registers: Corrected errors in register $4127 reference data.
26 April 2021
- 04:4904:49, 26 April 2021 diff hist +411 m Famicom Network System →Commands Written by the Famicom to CPU2: Cleanup
- 02:5502:55, 26 April 2021 diff hist −14 m Famicom Network System →Commands Written by the Famicom to CPU2
15 April 2021
- 22:5422:54, 15 April 2021 diff hist +113 Famicom Network System →CPU2 Known Registers: Added additional $4112 read bit observations.
- 22:4322:43, 15 April 2021 diff hist +716 Famicom Network System →CPU2 Known Registers: Added a few small observations.
12 April 2021
- 02:0902:09, 12 April 2021 diff hist +842 Famicom Network System →CPU2 Known Registers: Added newly-found info about IRQ timer in registers $4104,5,6,7 and $412F.6. It is similar to the NMI timer found by Joe.
- 00:3300:33, 12 April 2021 diff hist +224 m Famicom Network System →CPU2 Known Registers: Update "Read Has Data" column and change "(unknown)" read bits to "(unlikely to exist)" based on observed internal open bus behavior.
11 April 2021
- 23:3523:35, 11 April 2021 diff hist +318 Famicom Network System →Commands Written by the Famicom to CPU2: Cleanup.
- 23:0323:03, 11 April 2021 diff hist +40 Famicom Network System →CPU2 Known Registers: Added $4102.0 = NMI timer loop.
- 22:4322:43, 11 April 2021 diff hist +683 Famicom Network System →CPU2 Known Registers: Added info found about timer NMI.
10 April 2021
- 20:5120:51, 10 April 2021 diff hist +59 Famicom Network System →RF5A18 Internal 65C02 CPU: Measured CPU2 clock speed and found that it is 2.4576MHz.
7 April 2021
- 20:4920:49, 7 April 2021 diff hist −76 Famicom Network System Undo revision 18582: Theoretically pins 43-46 could be A8-A11, I don't want to exclude that.
- 20:4320:43, 7 April 2021 diff hist +76 Famicom Network System →Disk Drive Support: Updated statement about internal DRAM, not really possible.
6 April 2021
- 22:4022:40, 6 April 2021 diff hist +54 Famicom Network System →CPU2 Known Registers: Added clock source theory to Joe's awesome NMI findings.
5 April 2021
- 02:3802:38, 5 April 2021 diff hist 0 m Famicom Network System →RF5A18 CPU2 / Modem Controller: Corrected error I made on Jan 29, 2021 where RF5A18 pin 40 lost its (n/c) label.
4 April 2021
- 20:0120:01, 4 April 2021 diff hist +448 Famicom Network System Updated modem signals
2 April 2021
- 23:1623:16, 2 April 2021 diff hist +1,629 Famicom Network System →CPU2 Commands: Added table for connection status byte used in $80,81,82 response commands.
- 16:2616:26, 2 April 2021 diff hist +87 Famicom Network System →Commands Written by the Famicom to CPU2: Added $80/$81/$82 status bytes found in CPU2 ROM.
- 15:5715:57, 2 April 2021 diff hist +1,509 Famicom Network System →CPU2 Commands: Added some more CPU2 response commands.
1 April 2021
- 23:1423:14, 1 April 2021 diff hist +2,056 m Famicom Network System →Known Registers: Added more collapsible wikitables to hide messy reference data.
- 02:5402:54, 1 April 2021 diff hist +2,656 m Famicom Network System →CPU2 Known Registers: Hid a bunch of messy stuff inside collapsed tables
- 02:2202:22, 1 April 2021 diff hist +1,281 Famicom Network System →Commands Written by the Famicom to CPU2: Added disassembly of JRA-PAT's use of $7D, put disassemblies into collapsed wikitables.
- 00:2900:29, 1 April 2021 diff hist +20 m Famicom Network System →Commands Written by the Famicom to CPU2
31 March 2021
- 23:5323:53, 31 March 2021 diff hist +430 Famicom Network System →CPU2 Commands: Added some more CPU2 messages observed from JRA-PAT and added revisions.
- 05:1405:14, 31 March 2021 diff hist +186 Famicom Network System →Commands Written by the Famicom to CPU2: Improved Command $7D example disassembly
- 04:4204:42, 31 March 2021 diff hist +471 Famicom Network System →Commands Written by the Famicom to CPU2: Added disassembly of arbitrary code that Super Mario Club writes with command $7D.
30 March 2021
- 01:0201:02, 30 March 2021 diff hist +418 Famicom Network System →CPU2 Commands: Added examples of commands $03 and $7D from Super Mario Club
