User contributions for Ben Boldt
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1 January 2019
- 18:3318:33, 1 January 2019 diff hist +151 Talk:MMC5 →PRG Bankswitching
22 December 2018
- 01:2501:25, 22 December 2018 diff hist +78 Namcot 163 family pinout Updated footnote on pin 34. This pin appears as an input. I drove this pin with 100 Hz square wave while writing randomly to registers. I did not observe 100 Hz coming out on any other pin.
- 00:2700:27, 22 December 2018 diff hist +425 Namcot 163 family pinout Marked pin 34 as unknown, improved ASCII graphics.
21 December 2018
- 23:3923:39, 21 December 2018 diff hist +6 Namcot 163 family pinout Added info about pins 22 and 44.
- 23:3723:37, 21 December 2018 diff hist +164 INES Mapper 019 Added info about pins 22 and 44.
20 December 2018
- 22:1822:18, 20 December 2018 diff hist +209 MMC5 Added new findings from krzysiobal
17 December 2018
- 22:3922:39, 17 December 2018 diff hist +185 MMC5 →Vertical Split Mode ($5200): Added info about possible split screen mode in ending sequence of Bandit Kings of Ancient China.
8 December 2018
- 00:2700:27, 8 December 2018 diff hist +207 MMC5 →Unknown Register ($5800, write only): Updating with new info/clues
- 00:1800:18, 8 December 2018 diff hist +83 MMC5 →CL3 / SL3 Data Direction and Output Data ($5207 write only): Updated with new findings.
7 December 2018
- 01:5101:51, 7 December 2018 diff hist +151 MMC5 →Overview: Added info about reset detection.
6 December 2018
- 05:4605:46, 6 December 2018 diff hist −32 MMC5 pinout Showing SL3 & CL3 as bidirectional pins.
- 03:4003:40, 6 December 2018 diff hist −246 m MMC5 →CL3 / SL3 Status ($5208 read/write): Removed extra info that is no longer useful.
- 03:3803:38, 6 December 2018 diff hist +236 MMC5 Improved CL3/SL3 register descriptions with new findings
- 03:0303:03, 6 December 2018 diff hist +116 MMC5 →Unknown Register ($5207 write only)
- 02:1602:16, 6 December 2018 diff hist +682 MMC5 Added new findings from VCC current spike testing tonight.
25 November 2018
- 22:2422:24, 25 November 2018 diff hist +180 MMC5 →PRG Bankswitching: Grayed out boxes in the PRG bankswitching table where it can't be used due to /CS.
- 19:0219:02, 25 November 2018 diff hist +84 MMC5 →PRG Bankswitching: Additional clarity, filled in some RAM ?s
- 02:4802:48, 25 November 2018 diff hist +1,412 MMC5 →PRG Bankswitching: I have made improvements based on feedback in the forum.
23 November 2018
- 19:5819:58, 23 November 2018 diff hist +58 m MMC5 →PRG Bankswitching: Made table prettier.
- 19:0519:05, 23 November 2018 diff hist +721 MMC5 →PRG Bankswitching: Details about how the bits of the bankswitch registers physically correspond to PRG address bits.
- 18:4018:40, 23 November 2018 diff hist +126 MMC5 →PRG Bankswitching: Change order of modes, default/least complicated mode 3 first and then progressing to mode 0 now. Also noted for "Ignored" which register covers it.
- 18:3218:32, 23 November 2018 diff hist 0 m MMC5 →PRG Bankswitching
- 18:3118:31, 23 November 2018 diff hist +1,084 MMC5 →PRG Bankswitching: Renamed and added table
- 17:3917:39, 23 November 2018 diff hist +406,957 User:Ben Boldt No edit summary
21 November 2018
- 17:2117:21, 21 November 2018 diff hist +224 MMC5 →Overview: Added info about system reset detection.
20 November 2018
- 22:5222:52, 20 November 2018 diff hist +4 m MMC5 pinout Missed one
- 22:5022:50, 20 November 2018 diff hist −1,822 MMC5 pinout Added 'R's to the pinout for RAM connections. Removed redundant pinout.
13 November 2018
- 17:2317:23, 13 November 2018 diff hist +1 MMC5 Increased max PRG-RAM spec to 128k
- 00:1600:16, 13 November 2018 diff hist −288 MMC5 Undo revision 15822 by Ben Boldt (talk)
- 00:0400:04, 13 November 2018 diff hist +288 MMC5 Added info about bank register RAM mode not caring about PRG Mode
4 November 2018
- 18:3518:35, 4 November 2018 diff hist +2 MMC5 pinout Removed assumption that pin 75 is a /CE pin. There is strong evidence that it is a RAM /WE or /CE.
- 16:0816:08, 4 November 2018 diff hist +465 MMC5 pinout Labeled pin 75 as possibly PRG RAM 2 /CE, also added legend to pinout.
31 October 2018
- 01:2501:25, 31 October 2018 diff hist +2 m MMC5 No edit summary
- 01:2401:24, 31 October 2018 diff hist +248 MMC5 Added register $5800 as pointed out by Bregalad.
29 October 2018
- 00:5800:58, 29 October 2018 diff hist +630 MMC5 audio →Pin 2 DAC Characteristic: Added info about constant current
19 October 2018
- 18:4718:47, 19 October 2018 diff hist +74 MMC5 audio →Pin 2 DAC Characteristic
- 18:4218:42, 19 October 2018 diff hist +31 MMC5 audio →Pin 2 DAC Voltages: Updated to show observations considering AVcc
- 18:3618:36, 19 October 2018 diff hist 0 File:MMC5 DAC Characteristic.png Ben Boldt uploaded a new version of File:MMC5 DAC Characteristic.png current
- 18:0118:01, 19 October 2018 diff hist +180 MMC5 audio →Pin 2 DAC Voltages: Added additional DAC observation
18 October 2018
- 22:2022:20, 18 October 2018 diff hist −1 MMC5 pinout Took away question marks from Pin 2 -- verified and measured this pin.
- 22:1822:18, 18 October 2018 diff hist +229 MMC5 audio →Raw PCM ($5011): Added specifics about DAC voltage
- 22:1422:14, 18 October 2018 diff hist 0 N File:MMC5 DAC Characteristic.png No edit summary
- 16:5816:58, 18 October 2018 diff hist +145 MMC5 →Unknown Register ($5208 read): Update per findings from krzysiobal
17 October 2018
- 17:1017:10, 17 October 2018 diff hist +61 MMC5 →8x8 to 16 Multiplier ($5205, $5206 read/write): Made clear that this is an unsigned multiply.
15 October 2018
- 22:1422:14, 15 October 2018 diff hist +174 MMC5 - Scanline detection/counting: Reorganized, reworded. Hardware timer: added detail, reading $5209 while running = $00.
- 00:5700:57, 15 October 2018 diff hist 0 m MMC5 →Write
- 00:5600:56, 15 October 2018 diff hist +108 MMC5 →Write: clarification
- 00:5200:52, 15 October 2018 diff hist +101 MMC5 →Unknown Register ($5208 read): Added note about multiplier test vs. this register
- 00:4800:48, 15 October 2018 diff hist +847 MMC5 →16-bit Hardware Timer with IRQ ($5209 read/write, $520A write): More updates from krzysiobal
14 October 2018
- 20:0620:06, 14 October 2018 diff hist 0 m MMC5 →Hardware: Typo fix.
