User contributions for Ulfalizer
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24 May 2013
- 17:2417:24, 24 May 2013 diff hist +51 N File:Vis areas.png Different areas for Visual 6502/2C02/2A03 tutorial.
23 May 2013
- 05:4605:46, 23 May 2013 diff hist +11 APU Triangle Be more specific about what Mega Man 2 does
- 05:1805:18, 23 May 2013 diff hist +357 APU Triangle Add note about what causes popping sounds in the triangle in some games and how they can be eliminated in an emulator
22 May 2013
- 20:3720:37, 22 May 2013 diff hist +17 PPU pinout Explain AD abbreviation
- 20:3420:34, 22 May 2013 diff hist +99 m Talk:PPU pinout Add qualification :P
- 20:3220:32, 22 May 2013 diff hist +16 PPU pinout Call the control register PPUCTRL and add link to PPU registers page
- 20:2020:20, 22 May 2013 diff hist −2 m Talk:PPU pinout s/inputs/pins/
- 20:1820:18, 22 May 2013 diff hist +450 Talk:PPU pinout No edit summary
- 19:4519:45, 22 May 2013 diff hist +60 CPU Add nanoseconds per cycle for the different CPU frequencies
- 18:1818:18, 22 May 2013 diff hist +12 m PPU No edit summary
- 18:0418:04, 22 May 2013 diff hist +523 Talk:PPU pinout Rename some pins?
- 17:5917:59, 22 May 2013 diff hist +62 PPU pinout Add link to wiring diagram
- 17:5617:56, 22 May 2013 diff hist +23 PPU pinout Explain ALE abbreviation
- 17:5517:55, 22 May 2013 diff hist +124 PPU pinout Clarify the CPU side of things
- 17:4917:49, 22 May 2013 diff hist +80 PPU pinout /WR does not assert for writes to the palette
- 17:3017:30, 22 May 2013 diff hist −32 PPU pinout ALE doesn't "tell the PPU" - it's an output pin
- 17:2417:24, 22 May 2013 diff hist +87 PPU pinout Add some more ALE details
- 17:1917:19, 22 May 2013 diff hist +55 PPU pinout Add link to 'PPU rendering' for ALE details
- 17:1617:16, 22 May 2013 diff hist +52 PPU Add pinout link
- 13:4613:46, 22 May 2013 diff hist −6 6502 instructions 'CPU interrupt quirks' was moved to 'CPU interrupts'
- 13:4513:45, 22 May 2013 diff hist −8 Emulator tests 'CPU interrupt quirks' was moved to 'CPU interrupts'
- 13:4413:44, 22 May 2013 diff hist −33 CPU pinout 'CPU interrupt quirks' was moved to 'CPU interrupts'
- 13:4313:43, 22 May 2013 diff hist −6 CPU 'CPU interrupt quirks' was moved to 'CPU interrupts'
- 13:4113:41, 22 May 2013 diff hist 0 m Talk:CPU interrupts Ulfalizer moved page Talk:CPU interrupt quirks to Talk:CPU interrupts: It is about more than just "quirks"
- 13:4113:41, 22 May 2013 diff hist +33 N Talk:CPU interrupt quirks Ulfalizer moved page Talk:CPU interrupt quirks to Talk:CPU interrupts: It is about more than just "quirks" current
- 13:4113:41, 22 May 2013 diff hist +28 N CPU interrupt quirks Ulfalizer moved page CPU interrupt quirks to CPU interrupts: It is about more than just "quirks" current
- 13:4113:41, 22 May 2013 diff hist 0 m CPU interrupts Ulfalizer moved page CPU interrupt quirks to CPU interrupts: It is about more than just "quirks"
- 13:2213:22, 22 May 2013 diff hist +47 CPU pinout Specify that every cycle is either a read or a write cycle
- 13:2013:20, 22 May 2013 diff hist +233 CPU pinout Add some more timing details for Axx, Dx, and R/W (confirmed in Visual 6502)
- 12:5912:59, 22 May 2013 diff hist +500 N Talk:CPU interrupts Add some relevant Visual 6502 links so I don't lose them
- 12:4612:46, 22 May 2013 diff hist +110 CPU interrupts Interrupt polling occurs during φ1 (confirmed in Visual 6502)
- 12:3512:35, 22 May 2013 diff hist +189 CPU pinout Clarify that φ1 and φ2 high denote the first and second phases of each CPU cycle
15 May 2013
- 09:3109:31, 15 May 2013 diff hist −6 PPU rendering s/VRAM data input pins/VRAM data pins/
- 07:0507:05, 15 May 2013 diff hist +32 PPU rendering VRAM addresses are 14 bits long, not 16 bits
- 06:5606:56, 15 May 2013 diff hist +14 PPU rendering VRAM data can also be written by the PPU (on demand from the CPU)
- 06:5106:51, 15 May 2013 diff hist +839 PPU rendering Explain why VRAM reads take two PPU cycles
- 06:0606:06, 15 May 2013 diff hist +1 INES Mapper 004 Link to PPU Rendering instead of directly to the frame timing diagram
- 06:0206:02, 15 May 2013 diff hist +700 PPU rendering Add details on PPU address bus contents (derived from Visual 2C02)
9 May 2013
- 14:4314:43, 9 May 2013 diff hist +115 APU DMC Enumerate things that can affect the counter
- 14:3514:35, 9 May 2013 diff hist +47 APU DMC Clarify that the rate only affects automatic sample playback
- 14:2714:27, 9 May 2013 diff hist +220 APU Add output conditions for the DMC channel
8 May 2013
- 19:5419:54, 8 May 2013 diff hist +208 APU DMC Clarify what the rate value specifies
- 17:1317:13, 8 May 2013 diff hist +3 m APU DMC Fix typo
7 May 2013
- 15:0315:03, 7 May 2013 diff hist +50 APU Sweep Sweep needs to be enabled too to adjust the period :P
6 May 2013
- 14:5614:56, 6 May 2013 diff hist +230 APU Sweep Note that the silencing overflow still happens with a shift count of zero (confirmed in Visual 2A03)
- 13:4313:43, 6 May 2013 diff hist +22 APU Pulse Small sweep clarification
- 12:3012:30, 6 May 2013 diff hist +45 APU Pulse Output conditions were missing timer >= 8
- 12:2412:24, 6 May 2013 diff hist +135 APU Triangle Specify exactly where the waveform clocking happens
- 12:1112:11, 6 May 2013 diff hist +7 APU Pulse Specify exactly where the waveform clocking happens
- 09:3609:36, 6 May 2013 diff hist +289 APU Sweep Clarify that the silencing-even-when-disabled behavior is only relevant for overflow
