User contributions for Ulfalizer
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22 May 2013
- 17:1617:16, 22 May 2013 diff hist +52 PPU Add pinout link
- 13:4613:46, 22 May 2013 diff hist −6 6502 instructions 'CPU interrupt quirks' was moved to 'CPU interrupts'
- 13:4513:45, 22 May 2013 diff hist −8 Emulator tests 'CPU interrupt quirks' was moved to 'CPU interrupts'
- 13:4413:44, 22 May 2013 diff hist −33 CPU pinout 'CPU interrupt quirks' was moved to 'CPU interrupts'
- 13:4313:43, 22 May 2013 diff hist −6 CPU 'CPU interrupt quirks' was moved to 'CPU interrupts'
- 13:4113:41, 22 May 2013 diff hist 0 m Talk:CPU interrupts Ulfalizer moved page Talk:CPU interrupt quirks to Talk:CPU interrupts: It is about more than just "quirks"
- 13:4113:41, 22 May 2013 diff hist +33 N Talk:CPU interrupt quirks Ulfalizer moved page Talk:CPU interrupt quirks to Talk:CPU interrupts: It is about more than just "quirks" current
- 13:4113:41, 22 May 2013 diff hist +28 N CPU interrupt quirks Ulfalizer moved page CPU interrupt quirks to CPU interrupts: It is about more than just "quirks" current
- 13:4113:41, 22 May 2013 diff hist 0 m CPU interrupts Ulfalizer moved page CPU interrupt quirks to CPU interrupts: It is about more than just "quirks"
- 13:2213:22, 22 May 2013 diff hist +47 CPU pinout Specify that every cycle is either a read or a write cycle
- 13:2013:20, 22 May 2013 diff hist +233 CPU pinout Add some more timing details for Axx, Dx, and R/W (confirmed in Visual 6502)
- 12:5912:59, 22 May 2013 diff hist +500 N Talk:CPU interrupts Add some relevant Visual 6502 links so I don't lose them
- 12:4612:46, 22 May 2013 diff hist +110 CPU interrupts Interrupt polling occurs during φ1 (confirmed in Visual 6502)
- 12:3512:35, 22 May 2013 diff hist +189 CPU pinout Clarify that φ1 and φ2 high denote the first and second phases of each CPU cycle
15 May 2013
- 09:3109:31, 15 May 2013 diff hist −6 PPU rendering s/VRAM data input pins/VRAM data pins/
- 07:0507:05, 15 May 2013 diff hist +32 PPU rendering VRAM addresses are 14 bits long, not 16 bits
- 06:5606:56, 15 May 2013 diff hist +14 PPU rendering VRAM data can also be written by the PPU (on demand from the CPU)
- 06:5106:51, 15 May 2013 diff hist +839 PPU rendering Explain why VRAM reads take two PPU cycles
- 06:0606:06, 15 May 2013 diff hist +1 INES Mapper 004 Link to PPU Rendering instead of directly to the frame timing diagram
- 06:0206:02, 15 May 2013 diff hist +700 PPU rendering Add details on PPU address bus contents (derived from Visual 2C02)
9 May 2013
- 14:4314:43, 9 May 2013 diff hist +115 APU DMC Enumerate things that can affect the counter
- 14:3514:35, 9 May 2013 diff hist +47 APU DMC Clarify that the rate only affects automatic sample playback
- 14:2714:27, 9 May 2013 diff hist +220 APU Add output conditions for the DMC channel
8 May 2013
- 19:5419:54, 8 May 2013 diff hist +208 APU DMC Clarify what the rate value specifies
- 17:1317:13, 8 May 2013 diff hist +3 m APU DMC Fix typo
7 May 2013
- 15:0315:03, 7 May 2013 diff hist +50 APU Sweep Sweep needs to be enabled too to adjust the period :P
6 May 2013
- 14:5614:56, 6 May 2013 diff hist +230 APU Sweep Note that the silencing overflow still happens with a shift count of zero (confirmed in Visual 2A03)
- 13:4313:43, 6 May 2013 diff hist +22 APU Pulse Small sweep clarification
- 12:3012:30, 6 May 2013 diff hist +45 APU Pulse Output conditions were missing timer >= 8
- 12:2412:24, 6 May 2013 diff hist +135 APU Triangle Specify exactly where the waveform clocking happens
- 12:1112:11, 6 May 2013 diff hist +7 APU Pulse Specify exactly where the waveform clocking happens
- 09:3609:36, 6 May 2013 diff hist +289 APU Sweep Clarify that the silencing-even-when-disabled behavior is only relevant for overflow
- 09:0909:09, 6 May 2013 diff hist +88 APU Length Counter Constant volume flag was missing, making it look like the volume/envelope field is 5 bits long. Also make consistent with main page by using 'v' instead of 'e'.
- 09:0209:02, 6 May 2013 diff hist +17 APU Length Counter The triangle halt flag was renamed to linear counter reload flag
5 May 2013
- 14:0314:03, 5 May 2013 diff hist +38 APU Sweep Small silencing clarification
- 13:2213:22, 5 May 2013 diff hist +68 APU Envelope Clarify when the envelope counter decrement occurs
- 12:4312:43, 5 May 2013 diff hist +3 m APU Sweep Add an 'is'
- 12:4012:40, 5 May 2013 diff hist +389 APU Sweep Describe exactly when the period update happens and use the internal version of what's going in instead of the "clocked before reload" version (as it isn't any more complicated)
- 12:1112:11, 5 May 2013 diff hist −4 m APU Length Counter Fix typo
- 09:4909:49, 5 May 2013 diff hist +77 APU Sweep Internally, the target period is calculated continuously by the adder
- 09:2809:28, 5 May 2013 diff hist −99 APU Length Counter Ops... the length counter load values in the table are already adjusted to account for the becomes zero vs. is zero behavior
- 08:3808:38, 5 May 2013 diff hist +50 APU Length Counter Clarify that the clock-when-zero silencing behavior works intuitively with the halt flag too
- 08:1008:10, 5 May 2013 diff hist +10 m APU Length Counter s/APU clock/frame counter clock/
- 08:0708:07, 5 May 2013 diff hist +526 APU Length Counter The length counter period might be off by one if you just compare against zero (confirmed in Visual 2A03)
4 May 2013
- 13:5513:55, 4 May 2013 diff hist +1 m APU s/pulse channel/pulse channels/
- 09:0909:09, 4 May 2013 diff hist +504 PPU registers Use fancy-schmancy line drawing characters
- 08:2708:27, 4 May 2013 diff hist +27 m APU Rephrase pulse silencing exceptions a bit
- 08:1608:16, 4 May 2013 diff hist +50 m APU Clarify that channels play iff length counters > 0 in the abstract model
- 08:1008:10, 4 May 2013 diff hist +556 APU Add an overview of when channels will play (bit redundant, but imo justified in this case)
- 07:3307:33, 4 May 2013 diff hist 0 m APU Envelope Missed an s/N/V/