User contributions for Quietust
From NESdev Wiki
Jump to navigationJump to search
15 November 2011
- 00:5500:55, 15 November 2011 diff hist −3 m Talk:APU DMC No edit summary
- 00:4500:45, 15 November 2011 diff hist +247 m Talk:APU DMC No edit summary
14 November 2011
- 22:5522:55, 14 November 2011 diff hist +2 m Talk:APU DMC No edit summary
- 22:5522:55, 14 November 2011 diff hist +893 Talk:APU DMC have you forgotten that the Visual 2A03 exists?
- 01:4501:45, 14 November 2011 diff hist −1,881 m Bandai EPROM mapper Redirected page to Bandai FCG board current
9 November 2011
- 18:5018:50, 9 November 2011 diff hist −1 m Cartridge and mappers' history people need to learn proper spelling and grammar...
- 18:5018:50, 9 November 2011 diff hist −197 m Cartridge and mappers' history formatting
22 October 2011
- 18:1418:14, 22 October 2011 diff hist +16 m Talk:CPU power up state revised from visual2a03
- 18:0518:05, 22 October 2011 diff hist +60 m Talk:CPU pinout No edit summary
18 October 2011
- 14:5114:51, 18 October 2011 diff hist +213 N File:Vramaddr.jpg VRAM address register within the PPU, with annotations for write enables and data inputs for $2000/$2005/$2006 and the two T->V signals. Everything appears to be consistent with the skinny on NES scrolling. current
17 October 2011
- 23:4223:42, 17 October 2011 diff hist +212 Talk:Power Pad No edit summary
15 October 2011
- 02:2202:22, 15 October 2011 diff hist −24 m User:Quietust Visual6502.org's depackager/delayerer has been unavailable for the past 2 months and is expected to remain unavailable until "early next year", so no visual 2C02 until then :(
11 October 2011
- 16:5216:52, 11 October 2011 diff hist 0 m Accuracy pretty sure this is supposed to be $2007...
28 September 2011
- 17:5917:59, 28 September 2011 diff hist +668 N Talk:NTSC video cursory examination of the PPU's video signal generator
16 September 2011
- 18:2818:28, 16 September 2011 diff hist +673 Talk:CPU pinout just tested pin 30 with my CopyNES, and it DOES enable extra I/O registers
14 September 2011
- 19:5819:58, 14 September 2011 diff hist +175 Talk:CPU pinout was that actually verified?
13 September 2011
- 01:4801:48, 13 September 2011 diff hist +79 m User:Quietust alternate contact
12 September 2011
- 00:5800:58, 12 September 2011 diff hist −2 m User:Quietust No edit summary
2 September 2011
- 03:2803:28, 2 September 2011 diff hist +75 m File:2a03 map.jpg No edit summary
- 03:2703:27, 2 September 2011 diff hist +142 m User:Quietust Visual 2A03 URL changed; also, 2C02 is in progress (though stalled for the past 3 weeks, waiting for the chip to be delayered)
26 August 2011
- 21:2821:28, 26 August 2011 diff hist +8 m Mirroring →4-screen VRAM: this too
- 21:2721:27, 26 August 2011 diff hist +2 m Mirroring →Single-Screen: I'm assuming this is what you meant here...
- 02:2002:20, 26 August 2011 diff hist +305 Talk:NES 2.0 No edit summary
14 July 2011
- 03:1003:10, 14 July 2011 diff hist +164 Talk:CPU pinout →M2: new section
13 July 2011
- 12:4112:41, 13 July 2011 diff hist +212 m Talk:APU Frame Counter No edit summary
- 12:3712:37, 13 July 2011 diff hist +188 m Talk:APU Frame Counter No edit summary
- 03:3603:36, 13 July 2011 diff hist −2 m APU Frame Counter No edit summary
- 03:2003:20, 13 July 2011 diff hist +256 Talk:APU Frame Counter more info
- 03:1603:16, 13 July 2011 diff hist 0 APU Frame Counter make them actually APU cycles...
- 03:1403:14, 13 July 2011 diff hist −17 APU Frame Counter it takes 2 CPU cycles (1 APU cycle) to reset, not 2 APU cycles
12 July 2011
- 19:3319:33, 12 July 2011 diff hist +453 Talk:APU Frame Counter No edit summary
- 13:0713:07, 12 July 2011 diff hist +91 Talk:APU Frame Counter No edit summary
10 July 2011
- 21:1421:14, 10 July 2011 diff hist −237 APU Frame Counter there is NO 240Hz divider - the frame counter is a 15-bit counter (LFSR) that generates triggers at each cycle count; also, subtract 3 from cycle counts because of the reload delay on $4017 write
6 July 2011
- 03:3703:37, 6 July 2011 diff hist +39 m PPU sprite evaluation explain why the sprite engine is seemingly idle during these points - it's waiting for other things to happen within the PPU
30 June 2011
- 02:1402:14, 30 June 2011 diff hist +92 m User:Quietust No edit summary
29 June 2011
- 18:5718:57, 29 June 2011 diff hist +55 m Talk:APU Frame Counter clarify
- 18:4118:41, 29 June 2011 diff hist +308 m Talk:APU Frame Counter No edit summary
15 June 2011
- 12:5812:58, 15 June 2011 diff hist −132 m Emulators duplicate
8 June 2011
- 16:4116:41, 8 June 2011 diff hist +16 m Talk:CPU power up state No edit summary
- 16:4016:40, 8 June 2011 diff hist +1,401 N Talk:CPU power up state using my previous trace of the reset line combined with the "regions" image overlay
- 02:1202:12, 8 June 2011 diff hist +63 m File:2a03 map.jpg there's now a layer image that highlights all of these regions
6 June 2011
- 03:0303:03, 6 June 2011 diff hist −2 m Talk:APU DMC No edit summary
- 03:0303:03, 6 June 2011 diff hist +336 Talk:APU DMC No edit summary
18 May 2011
- 20:4220:42, 18 May 2011 diff hist +106 m Talk:APU Sweep No edit summary
- 20:4120:41, 18 May 2011 diff hist +27 m Talk:APU Sweep the triangle channel is clocked by every M1 pulse, and the rest of the APU is clocked either by even M1 pulses or odd M1 pulses (with a vast majority being even)
- 17:1517:15, 18 May 2011 diff hist +500 Talk:APU Sweep No edit summary
- 03:4903:49, 18 May 2011 diff hist +399 Talk:APU Sweep No edit summary
16 May 2011
- 02:2202:22, 16 May 2011 diff hist −274 File:2a03 map.jpg created a chip images index page on my site
14 May 2011
- 17:1617:16, 14 May 2011 diff hist +398 Talk:APU Sweep food for thought and/or research
- 16:5616:56, 14 May 2011 diff hist +14 APU Sweep clarify
