MMC1

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MMC1
SxROM
Company Nintendo, others
Games 390 in NesCartDB
Complexity ASIC
Boards SKROM, SLROM,
SNROM, others
Pinout MMC1 pinout
PRG ROM capacity 256K (512K)
PRG ROM window 16K + 16K fixed or 32K
PRG RAM capacity 32K
PRG RAM window 8K
CHR capacity 128K
CHR window 4K + 4K or 8K
Nametable mirroring H, V, or 1, switchable
Bus conflicts No
IRQ No
Audio No
iNES mappers 001, 105, 155

The Nintendo MMC1 is a mapper ASIC used in Nintendo's SxROM and NES-EVENT Game Pak boards. Most common SxROM boards are assigned to iNES Mapper 1. This chip first appeared in the April of 1987.

Banks

  • CPU $6000-$7FFF: 8 KB PRG RAM bank, (optional)
  • CPU $8000-$BFFF: 16 KB PRG ROM bank, either switchable or fixed to the first bank
  • CPU $C000-$FFFF: 16 KB PRG ROM bank, either fixed to the last bank or switchable
  • PPU $0000-$0FFF: 4 KB switchable CHR bank
  • PPU $1000-$1FFF: 4 KB switchable CHR bank

Through writes to the MMC1 control register, it is possible for the program to swap the fixed and switchable PRG ROM banks or to set up 32 KB PRG bankswitching (like BNROM), but most games use the default setup, which is similar to that of UxROM.

Registers

Unlike almost all other mappers, the MMC1 is configured through a serial port in order to reduce pin count. CPU $8000-$FFFF is connected to a common shift register. Writing a value with bit 7 set ($80 through $FF) to any address in $8000-$FFFF clears the shift register to its initial state. To change a register's value, the CPU writes five times with bit 7 clear and a bit of the desired value in bit 0. On the first four writes, the MMC1 shifts bit 0 into a shift register. On the fifth write, the MMC1 copies bit 0 and the shift register contents into an internal register selected by bits 14 and 13 of the address, and then it clears the shift register. Only on the fifth write does the address matter, and even then, only bits 14 and 13 of the address matter because the mapper registers are incompletely decoded like the PPU registers. After the fifth write, the shift register is cleared automatically, so a write to the shift register with bit 7 on to reset it is not needed.

When the CPU writes to the serial port on consecutive cycles, the MMC1 ignores all writes but the first. This happens when the 6502 executes read-modify-write (RMW) instructions, such as DEC and ROR, by writing back the old value and then writing the new value on the next cycle. At least Bill & Ted's Excellent Adventure resets the MMC1 by doing INC on a ROM location containing $FF; the MMC1 sees the $FF written back and ignores the $00 written on the next cycle.[1] The reason for this is that the MMC1 has explicit logic to disregard any write cycle following another write cycle. The location of the writes is not relevant, for example even a write to $8000 happening one cycle after a write to $7fff will be ignored by the MMC1, in practice such a thing cannot be made with a 6502 processor.[2]

To switch a bank, a program will execute code similar to the following: 

;
; Sets the switchable PRG ROM bank to the value of A.
;
              ;  A          MMC1_SR  MMC1_PB
setPRGBank:   ;  000edcba    10000             Start with an empty shift register (SR).  The 1 is used
  sta $E000   ;  000edcba -> a1000             to detect when the SR has become full.
  lsr a       ; >0000edcb    a1000
  sta $E000   ;  0000edcb -> ba100
  lsr a       ; >00000edc    ba100
  sta $E000   ;  00000edc -> cba10
  lsr a       ; >000000ed    cba10
  sta $E000   ;  000000ed -> dcba1             Once a 1 is shifted into the last position, the SR is full.
  lsr a       ; >0000000e    dcba1             
  sta $E000   ;  0000000e    dcba1 -> edcba    A write with the SR full copies D0 and the SR to a bank register
              ;              10000             ($E000-$FFFF means PRG bank number) and then clears the SR.
  rts

But because only the fifth write sets the destination register, the following equivalent (if obfuscated) subroutine changes the PRG ROM bank in the same manner: 

setPRGBank:
  sta $8765
  lsr a
  sta $FACE
  lsr a
  sta $BA11
  lsr a
  sta $AD2E
  lsr a
  sta $EAD5
  rts

Load register ($8000-$FFFF)

7  bit  0
---- ----
Rxxx xxxD
|       |
|       +- Data bit to be shifted into shift register, LSB first
+--------- 1: Reset shift register and write Control with (Control OR $0C),
              locking PRG ROM at $C000-$FFFF to the last bank.

Control (internal, $8000-$9FFF)

4bit0
-----
CPPMM
|||||
|||++- Mirroring (0: one-screen, lower bank; 1: one-screen, upper bank;
|||               2: vertical; 3: horizontal)
|++--- PRG ROM bank mode (0, 1: switch 32 KB at $8000, ignoring low bit of bank number;
|                         2: fix first bank at $8000 and switch 16 KB bank at $C000;
|                         3: fix last bank at $C000 and switch 16 KB bank at $8000)
+----- CHR ROM bank mode (0: switch 8 KB at a time; 1: switch two separate 4 KB banks)

Although some tests have found that all versions of the MMC1 seems to reliably power on in the last bank (by setting the "PRG ROM bank mode" to 3); other tests have found that this is fragile. Several commercial games have reset vectors every 32 KiB, but not every 16, so evidently PRG ROM bank mode 2 doesn't seem to occur randomly on power-up.

CHR bank 0 (internal, $A000-$BFFF)

4bit0
-----
CCCCC
|||||
+++++- Select 4 KB or 8 KB CHR bank at PPU $0000 (low bit ignored in 8 KB mode)

MMC1 can do CHR banking in 4KB chunks. Known carts with CHR RAM have 8 KiB, so that makes 2 banks. RAM vs ROM doesn't make any difference for address lines. For carts with 8 KiB of CHR (be it ROM or RAM), MMC1 follows the common behavior of using only the low-order bits: the bank number is in effect ANDed with 1.

CHR bank 1 (internal, $C000-$DFFF)

4bit0
-----
CCCCC
|||||
+++++- Select 4 KB CHR bank at PPU $1000 (ignored in 8 KB mode)

PRG bank (internal, $E000-$FFFF)

4bit0
-----
RPPPP
|||||
|++++- Select 16 KB PRG ROM bank (low bit ignored in 32 KB mode)
+----- PRG RAM chip enable (0: enabled; 1: disabled; ignored on MMC1A)

The high bit does not select a PRG ROM bank. MMC1 with 512K was supported by re-using a line from the CHR banking controls. (See below.)

Hardware

At least 6 different versions of the MMC1 are known to exist: MMC1, MMC1A, MMC1B1, MMC1B2, MMC1B3, and MMC1C. The known differences are as follows:

  • MMC1A: PRG RAM is always enabled. Two games abuse this lack of feature: they have been allocated to iNES Mapper 155.
  • MMC1B: PRG RAM is enabled by default.
  • MMC1C: PRG RAM is disabled by default.

The MMC1 most commonly exists in a 24-pin shrink-DIP package.

Boards using an MMC1 may contain a battery connected to the PRG RAM's power line to preserve the data. Boards doing so will allow extra circuitry to be used, with 2 diodes and 2 resistors. A diode is needed from both voltage sources: The battery and the NES 5V, so that one cannot supply current to the other, and there is a resistor in series with the battery as part of UL compliance. A pull-down resistor is needed on the CE line so that the SRAM is disabled when the MMC1 isn't powered. Finally, the battery powered SRAMs have an additional larger decoupling capacitor to make sure voltage transitions are smooth. Very early NES-SNROM-03 and lower revisions lacks that capcity, and saves are lost much more easily on those boards.

Nintendo transitioned from the original MMC1 (manufactured by ROHM) to the MMC1A (manufactured probably by Ricoh) around the 39th week of 1988. (Based on comparison of otherwise identical SMB/DH/WCTM carts from 38th and 39th weeks of '88)

AX5904 is a third-party clone of the MMC1A.

Variants

Because the higher CHR lines aren't used when the MMC1 mapper is used with a 8KB CHR RAM, those lines are sometimes put to other uses depending on the board :

SNROM

CHR bank 0 (internal, $A000-$BFFF)

4bit0
-----
ExxxC
|   |
|   +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
+----- PRG RAM disable (0: enable, 1: open bus)

CHR bank 1 (internal, $C000-$DFFF)

4bit0
-----
ExxxC
|   |
|   +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode)
+----- PRG RAM disable (0: enable, 1: open bus) (ignored in 8 KB mode)

Both the E bit and the R bit (in standard MMC1 registers) should be clear in order for the PRG RAM to be writable or readable. This bit is more "reliable" on authentic hardware as it is implemented even in older boards with older MMC1's, while the R bit was only introduced later. But because the E bit wasn't confirmed by the homebrew community until October 2010[3], emulators tend not to implement it.

SOROM, SUROM and SXROM

CHR bank 0 (internal, $A000-$BFFF)

4bit0
-----
PSSxC
||| |
||| +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
|++--- Select 8 KB PRG RAM bank
+----- Select 256 KB PRG ROM bank

CHR bank 1 (internal, $C000-$DFFF)

4bit0
-----
PSSxC
||| |
||| +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode)
|++--- Select 8 KB PRG RAM bank (ignored in 8 KB mode)
+----- Select 256 KB PRG ROM bank (ignored in 8 KB mode)

The SOROM board only implements the upper S bit, while the SUROM board only implements the P bit. For SXROM, the upper S (bit 3) selects the SRAM's A14, and the lower S (bit 2) selects A13[4].

The 256 KB PRG bank selection applies to all the PRG area, including the supposedly "fixed" bank.

In 4KB CHR bank mode, SNROM's E bit and SO/U/XROM's P and S bits in both CHR bank registers must be set to the same values, or the PRG ROM and/or RAM will be bankswitched/enabled as the PPU renders, in a similar fashion as MMC3's scanline counter. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the Control register.

SZROM

CHR bank 0 (internal, $A000-$BFFF)

4bit0
-----
RCCCC
|||||
|++++- Select 4 KB CHR ROM bank at PPU $0000 (low bit ignored in 8 KB mode)
+----- Select 8 KB PRG RAM bank

CHR bank 1 (internal, $C000-$DFFF)

4bit0
-----
RCCCC
|||||
|++++- Select 4 KB CHR ROM bank at PPU $1000 (ignored in 8 KB mode)
+----- Select 8 KB PRG RAM bank (ignored in 8 KB mode)

SZROM behaves similarly to SOROM, except that the PRG RAM bank is a controlled by a different bit, and enough CHR is present that 4K bankswitching is desirable. The only currently-known game on SZROM is A Ressha de Ikou.

SZROM can be detected by a NES2.0 header specifying 8K of PRG RAM, 8K of PRG NV RAM, and 16K or more of CHR.

iNES Mapper 001

iNES Mapper 001 is used to designate the SxROM boardset, all of which use Nintendo's MMC1.

Because some MMC1 boards (e.g. SOROM, SUROM and SXROM) used the upper CHR bank select lines instead to select additional PRG ROM or PRG RAM data: 

$A000 and $C000:
4bit0
-----
EDCBA
|||||
||||+- CHR A12
|||+-- CHR A13, if extant (CHR >= 16k)
||+--- CHR A14, if extant; and PRG RAM A14, if extant (PRG RAM = 32k)
|+---- CHR A15, if extant; and PRG RAM A13, if extant (PRG RAM >= 16k)
+----- CHR A16, if extant; and PRG ROM A18, if extant (PRG ROM = 512k)

The E bit also acts as a PRG RAM disable for SNROM (PRG ROM <= 256k, CHR RAM = 8k, PRG RAM = 8k), though this is merely for write protection and not strictly required for compatible emulation.

The D and C lines are swapped for SXROM (32k PRG RAM) here; the D line actually selects the upper SRAM address line, though this reversal might be irrelevant to an emulator's implementation.

NES 2.0 is required to specify PRG-RAM size. Without NES 2.0 the PRG-RAM size has to be assumed (32k may be sufficient for compatibility).

Boards designed for 32k PRG-ROM (SEROM, SHROM, and SH1ROM) do not connect PRG A14 to the MMC1, disabling PRG banking. For compatibility with these, the emulator may switch to PRG bank 0 at power-on. SIROM supports banked 32k PRG, however.

References

  1. ↑ 6502_cpu.txt. See the section labelled Instruction Timing, subsections Absolute addressing, Read-Modify-Write instructions
  2. ↑ http://forums.nesdev.org/viewtopic.php?f=9&t=8277&start=43
  3. ↑ Form topic: NES SNROM to 512K cart?
  4. ↑ Forum post: tracing the SXROM PCB

See also

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