APU registers

The following memory-mapped registers are used by the NES APU. They are write-only except $4015 which is read/write. Unused registers aren't listed.

For Famicom expansion audio registers, see also: Expansion audio

Address	7654.3210	Function
		Pulse 1 channel (write)
$4000	DDLC NNNN	Duty, loop envelope/disable length counter, constant volume, envelope period/volume
$4001	EPPP NSSS	Sweep unit: enabled, period, negative, shift count
$4002	LLLL LLLL	Timer low
$4003	LLLL LHHH	Length counter load, timer high (also resets duty and starts envelope)
		Pulse 2 channel (write)
$4004	DDLC NNNN	Duty, loop envelope/disable length counter, constant volume, envelope period/volume
$4005	EPPP NSSS	Sweep unit: enabled, period, negative, shift count
$4006	LLLL LLLL	Timer low
$4007	LLLL LHHH	Length counter load, timer high (also resets duty and starts envelope)
		Triangle channel (write)
$4008	CRRR RRRR	Length counter disable/linear counter control, linear counter reload value
$400A	LLLL LLLL	Timer low
$400B	LLLL LHHH	Length counter load, timer high (also reloads linear counter)
		Noise channel (write)
$400C	--LC NNNN	Loop envelope/disable length counter, constant volume, envelope period/volume
$400E	L--- PPPP	Loop noise, noise period
$400F	LLLL L---	Length counter load (also starts envelope)
		DMC channel (write)
$4010	IL-- FFFF	IRQ enable, loop sample, frequency index
$4011	-DDD DDDD	Direct load
$4012	AAAA AAAA	Sample address %11AAAAAA.AA000000
$4013	LLLL LLLL	Sample length %0000LLLL.LLLL0001
$4015	---D NT21	Control: DMC enable, length counter enables: noise, triangle, pulse 2, pulse 1 (write)
$4015	IF-D NT21	Status: DMC interrupt, frame interrupt, length counter status: noise, triangle, pulse 2, pulse 1 (read)
$4017	SD-- ----	Frame counter: 5-frame sequence, disable frame interrupt (write)