APU
The NES APU is the audio processing unit in the NES console which generates sound for games. It is implemented in the RP2A03 (NTSC) and RP2A07 (PAL) chips. Its registers are mapped in the range $4000-$4013, $4015 and $4017.
Overview
The APU has five channels: two pulse wave generators, a triangle wave, noise, and a delta modulation channel for playing DPCM samples.
Each channel has a variable-rate timer clocking a waveform generator, and various modulators driven by low-frequency clocks from the Frame Counter/Sequencer. The DMC plays samples while the other channels play waveforms. Each sub-unit of a channel generally runs independently and in parallel to other units, and modification of a channel's parameter usually affects only one sub-unit and doesn't take effect until that unit's next internal cycle begins.
The read/write status register allows channels to be enabled and disabled, and their current length counter status to be queried.
The outputs from all the channels are combined using a non-linear mixing scheme.
Notes
- This reference describes the abstract operation of the APU. The exact hardware implementation is not necessarily relevant to an emulator, but the Visual 2A03 project can be used to determine detailed information about the hardware implementation.
- The Famicom had an audio return loop on its catridge connector allowing extra audio from individual cartridges. See Expansion audio for details on the audio produced by various mappers.
- For a basic usage guide to the APU, see APU basics, or Nerdy Nights: APU overview.
Specification
Registers
| Registers | Channel | Units |
|---|---|---|
| $4000-$4003 | Pulse 1 | Timer, Length Counter, Envelope, Sweep |
| $4004-$4007 | Pulse 2 | Timer, Length Counter, Envelope, Sweep |
| $4008-$400B | Triangle | Timer, Length Counter, linear counter |
| $400C-$400F | Noise | Timer, Length Counter, Envelope, shift register w/ feedback |
| $4010-$4013 | DMC | Timer, memory reader, sample buffer, output unit |
| $4015 | All | Length Counter enable and status |
| $4017 | All | Frame Counter/Sequencer |
Pulse ($4000-4007)
- See APU Pulse
Triangle ($4008-400B)
- See APU Triangle
Noise ($400C-400F)
- See APU Noise
DMC ($4010-4013)
- See APU DMC
Status ($4015)
- See APU Status
Frame Sequencer ($4017)
| $4017 | MI-- ---- | Mode (M, 0 = 4-step, 1 = 5-step), IRQ inhibit flag (I) |
The frame sequencer is controlled by register $4017, and it drives the envelope, sweep, and length units on the pulse, triangle and noise channels. This sequencer ticks approximately 4 times per frame (240Hz), and executes either a 4 or 5 step cycle, depending how it is configured. It may optionally issue an IRQ on the last tick of each cycle.
The following diagram illustrates the two modes, selected by bit 7 of $4017:
mode 0: mode 1: function --------- ----------- ----------------------------- - - - f - - - - - IRQ (if bit 6 is clear) - l - l l - l - - Length counter and sweep e e e e e e e e - Envelope and linear counter
Both the 4 and 5-step modes operate at the same rate, but because the 5-step mode has an extra step, the effective update rate for individual units is slower in that mode (total update taking ~60Hz vs ~48Hz). Writing to $4017 will restart the cycle almost immediately (2 or 3 CPU cycles delay). Writing $4017 with bit 7 set will immediately clock all of its controlled units at the beginning of the 5-step cycle, but with bit 7 clear only the envelope and linear counter will be clocked.
Note that the frame sequencer is not exactly synchronized with the PPU NMI; it runs independently at a consistent rate which is approximately 240Hz. Some games (e.g. Super Mario Bros., Zelda) manually synchronize it by writing $C0 or $FF to $4017 once per frame.
Envelope
- See APU Envelope
Length Counter
Miscellaneous
- All APU channels have some form of frequency control. The term frequency is used where larger register value(s) correspond with higher frequencies, and the term period is used where smaller register value(s) correspond with higher frequencies.
- In the block diagrams, a gate takes the input on the left and outputs it on the right, unless the control input on top tells the gate to ignore the input and always output 0.
- Some APU units use one or more of the following building blocks:
- A divider outputs a clock every n input clocks, where n is the divider's period. It contains a counter which is decremented on the arrival of each clock. When the counter reaches 0, it is reloaded with the period and an output clock is generated. A divider can also be forced to reload its counter immediately, but this does not output a clock. When a divider's period is changed, the current count is not affected.
- A divider may be implemented as a down counter (5, 4, 3, ...) or as a linear feedback shift register (LFSR). The dividers in the pulse and triangle channels are linear down-counters. The dividers for noise, DMC, and the APU Frame Counter are implemented as LFSRs to save gates compared to the equivalent down counter.
- A sequencer continuously loops over a sequence of values or events. When clocked, the next item in the sequence is generated.
- A timer is used in each of the five channels to control the sound frequency. It contains a divider which is clocked by the CPU clock. The triangle channel's timer is clocked on every CPU cycle, but the pulse, noise, and DMC timers are clocked only on every second CPU cycle and thus produce only even periods.
