User:Zzo38/Mapper F
Registers
Registers are mapped at $5800-$5FFF, using the low four bits as a register number. There may be different registers for reading as for writing. The same registers are also mapped at $1800-$1FFF, however reading from those address may result in bus conflicts. Writing there is OK, though.
Therefore, the address mask is:
[0.01 1... .... xxxx]
$5800 (W)
[ESMM CCCC] |||| |||| |||| ++++--- CIRAM enable ||++-------- Nametable mirroring |+---------- CIRAM swap +----------- Enable console audio
If the "E" bit is cleared, then only the expansion audio is played, and the audio from 2A03 + microphone is disabled.
Nametable mirroring decides the connection of CIRAM A10, depending on "MM", and then that address line is XORed by "S", as follows:
- 00 = PA10
- 01 = PA11
- 10 = PA12
- 11 = PA13
The "CCCC" decides which sections of PPU address space are accessing CIRAM (if the bit is clear, CIRAM is used; if set, the CHR ROM/RAM in the cartridge is used):
- bit0 = $0000-$0FFF
- bit1 = $1000-$1FFF
- bit2 = $2000-$2FFF
- bit3 = $3000-$3EFF
$5800 (R)
[.... XXXX]
||||
++++--- 4-bit ADC
This register is a 4-bit ADC for the 2A03+microphone audio. Mute and expansion audio are not applied; it is the same audio signal as cartridge is receiving at first.
$5801 (W)
[VV.P PPPP] || | |||| || +-++++--- 16K PRG ROM bank at $8000-$BFFF ++---------- Video mode
$5802 (W)
[...P PPPP]
| ||||
+-++++--- 8K PRG ROM bank at $C000-$DFFF
This is actually the low 8K of a 16K bank, so the high 8K of a 16K bank cannot be mapped into $C000-$DFFF.
$5803 (W)
[.... .BBB]
|||
+++--- 8K PRG RAM bank at $6000-$7FFF
$5804
Same as register $580C, but for channel 1.
$5805
Same as register $580D, but for channel 1.
$5806
Same as register $580E, but for channel 1.
$5807 (W)
[HHHH LLLL] |||| |||| |||| ++++--- 4K CHR bank at $0000-$0FFF ++++-------- 4K CHR bank at $1000-$1FFF
If there is both CHR ROM and CHR RAM, then the high bit (bit3) of the bank number selects between ROM and RAM (ROM if cleared, RAM if set).
If CHR RAM is enabled but that address range is also set to CIRAM, then reading will read CIRAM, but writing will write both the CIRAM and the cartridge CHR RAM.
$5808
Same as register $580C, but for channel 2.
$5809
Same as register $580D, but for channel 2.
$580A
Same as register $580E, but for channel 2.
$580B (R/W)
This is ExRAM mode register.
$580C (W)
[P..W AAAA] | | |||| | | ++++--- AND mask | +-------- Waveform (0: saw, 1: square) +----------- Phase reset if bit is cleared
The waveform is used to determine the output values:
- Saw: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
- Square: 0 0 30 30 0 0 30 30 0 0 30 30 0 0 30 30 0 0 30 30 0 0 30 30 0 0 30 30 0 0 30 30
These values from the waveform are then taken, the AND mask is left shift by one and add one, and it is bitwise AND by the result, to determine the output level.
$580C (R)
[...P PPPP]
| ||||
+-++++--- Phase output
This register outputs the phase value from 0 to 31 which is the index into the waveform.
$580D (W)
[XXXX XXXX] |||| |||| ++++-++++--- Low bits of period of channel 3
$580E (W)
[XXXX XXXX] |||| |||| ++++-++++--- High bits of period of channel 3
$580F (W)
[HHHH LLLL] |||| |||| |||| ++++--- 4K CHR bank at $2000-$2FFF ++++-------- 4K CHR bank at $3000-$3EFF
If there is both CHR ROM and CHR RAM, then the high bit (bit3) of the bank number selects between ROM and RAM (ROM if cleared, RAM if set).
If CHR RAM is enabled but that address range is also set to CIRAM, then reading will read CIRAM, but writing will write both the CIRAM and the cartridge CHR RAM.
