User:Myask/MyaGrafx
"Perhaps someone should mock up a specification for a CPLD that only provides 8x8 attributes and nothing else."--Tepples
Sources
PPU rendering, Cartridge connector
Basic
As the cart only has CIRAM A10 piped through, one can't just remap part of CIRAM to supply the 256 bytes of attribute one needs for page 0.
So, for the basicmost case... PPU: --10 NT11 11yy yxxx is where attributes normally reside. To our advantage, the nametable byte precedes the attribute table byte. This allows at least the 8x8 tile to be detected: NT-fetch is PPU: --10 NTYY YyyX XXxx. (A0, A5 are what we want to know, as they're not in the AT fetch; A1,6 are the 16-px accounted for by which two bits within an attribute byte.). For this simple one, instead of storing the attribute data per-tile, it's arranged as usual: four tiles in a 32x32 are specified each byte, just that the game pak will return different byte depending on the X and Y tile evenness.
//pseudo-verilog
fall(PPU_/RD){
if (PPU_A13 & NAND(PPUA8, PPUA9) {AT_8X <= PPUA0; AT_8Y <= PPUA5} //NT-fetch
}
rise(M2){
if (~CPU_W & CPU_A15 == 1) //only have one visible register bit, so little decoding necessary: CPU$8xxx.
Mya_ATRAM_Enable <= CPU_D0;
}
Mya_ATRAM_A0-5 = PPU_A0-5; //don't really need to go through CPLD?
Mya_ATRAM_A6 = PPU_A12 ? PPU_A6: AT_8X; //write to PPU 0011 NT*0 YXyy yxxx, A8=0 is to dodge palettes.
Mya_ATRAM_A7 = PPU_A12 ? PPU_A7: AT_8Y;
Mya_ATRAM_A8-9 = PPU_A10-11; //NT-select. Also don't need to be routed through.
Mya_ATRAM_WR = PPU_WR & PPU_A13 & PPU_A12 & ~PPU_A8;
Mya_ATRAM_CE = PPU_A13 & (PPU_A12 ? (~PPU_A8) : PPU_A8) & PPU_A9 & (AT_8X | AT_8Y) & Mya_ATRAM_Enable;
CIRAM_CE = PPUA13 //NT/AT only
& (~PPUA12 | AND(PPUA8-11)) //disable for 30xx-3Exx to allow the writes to cart
& (AND(PPUA6-9) ? NOR(AT_8X | AT_8Y): 1); //and enable for the UL AT fetches and all NT fetches.
//also connect Mya_ATRAM_D0-7 to PPU_D0-7
Less basic
This mode of writing does not work if we want to extend to 8x1 attributes; there are three bits of attribute space to add and we only have three choices (00, 01, 10) of PPUADDR 8-9 for NT3. Even in two-screen mirroring, there is a small problem: but as we are relying on CIRAM for the first sliver of each section, one does not need to have duplicate write-access to those. One could remap $38** to what would have been in $3F**. Four-screen proves more problematic. Also problematic is determining the fine-Y. Brute-force method is to snoop for writes to PPU_SCROLL, as well as reads from PPU_STATUS and writes to PPU_ADDR to know the high-byte latch status. If we don't want to allow raster effects, which seems like a short-sighted decision, perhaps one could somehow divine where to begin from the dummy-fetch prerender scanline. In any case, it would basically require a scanline counter, at which point one would just add a few more bits of state to get a useful scanline-type interrupt, though if it shares the low three bits with the rendering portion it would be more of a NT-relative Y-coordinate interrupt...
