Talk:Errata
To-do list
Some things to add by people who know what these refer to:
PPU: must wait a couple of vblanks before chip is fully active
PPU: can't reliably write to ports more often than several CPU cycles apart
Page-crossing pointer quirks:
JMP ($nnnn)
($nn),Y
($nn,X) -- Blargg (talk) 18:03, 21 October 2013 (MST)
I don't understand this ceaveat
In horizontal or 4-screen mirroring, writing $2000 at the exact start of horizontal blanking may cause the PPU to start reading from the first pattern table instead of the second. (Workaround: Don't disable NMI during active picture. Instead, use a variable to lock out reentrant NMI.)
Can someone rewrite it with a better wording so that non-native english speakers understand it ?
Bregalad (talk) 05:12, 4 November 2013 (MST)
- Errata in the errata? Chalk it up to Muphry's law. --Tepples (talk) 15:54, 4 November 2013 (MST)
- This was the SMB bug where on 1/3 power-ons, the PPU alignment allows the mid-screen write to $2000 to interfere with the nametable selection on the next line if perfectly (unfortunately) timed. It results in one line of the screen being rendered with the wrong nametable. What do you think would help the wording, Bregalad? Rainwarrior (talk) 09:52, 5 November 2013 (MST)
OK now I think I understand the problem, but I don't see how the "workarround" proposed is related to the problem in any way - which leads me to think I might have misunderstanded the problem in the 1st place.
So my understanding is that, writing to $2000, in any scanline, at a particular PPU clock cycle, will force the nametable bit to '0', even if D0 of the data written to $2000 is 1. Is my understanding correct ? In this case the workarround would be sure to make write to $2000 early enough so they happen before HBlank, right ? I don't see why this is related to NMIs in any way.Bregalad (talk) 01:05, 23 May 2014 (MDT)
Unofficial instructions
I just want to point out that more games rely on not simply connecting CIRAM/CE to PPU/A13 than using unofficial instructions, and there are plenty of clones that disable that control. Furthermore, if they use a non-NMOS implementation of the CPU, many of the unofficial opcodes would require extra effort to implement.
On the other hand, the A53 cart contains two games that use the MUSE replay engine, which uses AXS and LAX (zz),y and I don't think we've had anyone unable to run it as a result. — Lidnariq (talk) 17:18, 12 December 2013 (MST)
