Talk:APU Sweep

Interesting fact: the 2 square channels are almost perfect mirror images of each other on the silicon, with one single difference: where one part of the 2nd channel's sweep unit takes as an input the (inverted) state of the Negate flag, the equivalent input in the 1st channel's sweep unit is hardwired to +5V. Said input is almost definitely the Carry Input flag, and it explains the difference in behavior. --Quietust 00:45, 10 May 2011 (UTC)

The RP2A03 may have originally been planned to permit periods as low as 4 - the current "silence on period < 8" behavior is accomplished by feeding bits 3-10 into a large NOR gate (if they're all 0, the channel is silenced), but there's another unconnected input for bit 2. It might be enlightening to test earlier versions of the chip. --Quietust 17:16, 14 May 2011 (UTC)

Does the sweep unit disable when the target period is greater than 3FF or greater than 7FF? --Drag 04:00, 17 May 2011 (UTC)