Talk:APU DMC

Similarly to the noise channel, the DPCM channel's frequency counter on the die is a 9-bit linear feedback shift register (with taps at the 5th and 9th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '100000000', the cycle counts (for NTSC) match once multiplied by 2. --Quietust 05:00, 23 January 2011 (UTC)

I suspect there's no "address increment", but another shift register. Just pay attention to the address wrap - if we had a counter, it would wrap to zero, but instead, it wraps to $8000, like ($10000 >> 1). --Zepper 01:49, 6 June 2011 (UTC)

The generated addresses are linear, and I don't think a shift register can do that. So I'm conjecturing an up-counter here. --Tepples 02:30, 6 June 2011 (UTC)

The DPCM address register is only 15 bits wide (with A15 being connected to the VCC rail @ 2850,5450), and the upper bit (A14) gets initialized to 1 (@ 2565,5365) instead of the last value written to $4012 (and the bottom 6 bits get initialized to 0, but we already know this). --Quietust 03:03, 6 June 2011 (UTC)