PPU pinout: Difference between revisions
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Rainwarrior (talk | contribs) (renaming CPU address A2-A0 to R2-R0 to avoid confusion between this and the PPU address which is also mostly using A to label pins?) |
Rainwarrior (talk | contribs) (adding CPU/PPU prefix to A instead of renaming CPU to R, suggested by bregalad) |
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=== Pin out === | === Pin out === | ||
.--\/--. | .--\/--. | ||
R/W -> |01 40| -- +5 | |||
D0 <> |02 39| -> ALE | |||
D1 <> |03 38| <> PPU AD0 | |||
D2 <> |04 37| <> PPU AD1 | |||
D3 <> |05 36| <> PPU AD2 | |||
D4 <> |06 35| <> PPU AD3 | |||
D5 <> |07 34| <> PPU AD4 | |||
D6 <> |08 33| <> PPU AD5 | |||
D7 <> |09 32| <> PPU AD6 | |||
CPU A2 -> |10 31| <> PPU AD7 | |||
CPU A1 -> |11 30| -> PPU A8 | |||
CPU A0 -> |12 29| -> PPU A9 | |||
/CS -> |13 28| -> PPU A10 | |||
EXT0 <> |14 27| -> PPU A11 | |||
EXT1 <> |15 26| -> PPU A12 | |||
EXT2 <> |16 25| -> PPU A13 | |||
EXT3 <> |17 24| -> /RD | |||
CLK -> |18 23| -> /WR | |||
/INT <- |19 22| <- /RST | |||
GND -- |20 21| -> VOUT | |||
`------' | `------' | ||
=== Signal description === | === Signal description === | ||
* R/W, Dx, | * R/W, Dx, CPU A0, A1, A2 are signals from the [[CPU pin out and signal description|CPU]]. CPU A2-A0 are tied to the corresponding CPU address pins and select the PPU register (0-7). | ||
* /CS is generated by the [[74139]] (address decoder) on the mainboard to map the PPU regs in the CPU memory range from $2000 to $3FFF. | * /CS is generated by the [[74139]] (address decoder) on the mainboard to map the PPU regs in the CPU memory range from $2000 to $3FFF. | ||
* EXTx allows the combination of two PPUs - setting the "slave" bit in the [[PPUCTRL]] ($2000) register causes the PPU to output palette indices to these pins, and clearing said bit causes it to instead read indices from these pins (and use them to select the background color). For the Vs. System and Playchoice PPUs, EXT0…2 are replaced with R, G, and B respectively. EXT3 is tied to ground; its functionality is unknown. | * EXTx allows the combination of two PPUs - setting the "slave" bit in the [[PPUCTRL]] ($2000) register causes the PPU to output palette indices to these pins, and clearing said bit causes it to instead read indices from these pins (and use them to select the background color). For the Vs. System and Playchoice PPUs, EXT0…2 are replaced with R, G, and B respectively. EXT3 is tied to ground; its functionality is unknown. | ||
| Line 31: | Line 31: | ||
* /INT is connected to the CPU's /NMI pin. | * /INT is connected to the CPU's /NMI pin. | ||
* ALE (Address Latch Enable) goes high at the beginning of a PPU VRAM access and is used to latch the lower 8 bits of the PPU's address bus; see the PPU address bus section of [[PPU rendering]]. It stays high for one PPU cycle. | * ALE (Address Latch Enable) goes high at the beginning of a PPU VRAM access and is used to latch the lower 8 bits of the PPU's address bus; see the PPU address bus section of [[PPU rendering]]. It stays high for one PPU cycle. | ||
* ADx (Address + Data) is the PPU's data bus, multiplexed with the lower 8 bits of the PPU's address bus. | * PPU ADx (Address + Data) is the PPU's data bus, multiplexed with the lower 8 bits of the PPU's address bus. | ||
* A8 | * PPU A8-A13 are the top 6 bits of the PPU's address bus. | ||
* /RD and /WR specify that the PPU is reading from or writing to VRAM. As an exception, writing to the internal palette range (3F00-3FFF) will not assert /WR. | * /RD and /WR specify that the PPU is reading from or writing to VRAM. As an exception, writing to the internal palette range (3F00-3FFF) will not assert /WR. | ||
* /RST resets certain parts of the chip to their initial power-on state: the clock divider, video phase generator, scanline/pixel counters, and the even/odd frame toggle. It also keeps several registers zeroed out for a full frame: [[PPUCTRL]], [[PPUMASK]] ($2001), [[PPUSCROLL]] ($2005; the VRAM address latch "T", fine X scroll, and the H/V toggle), and the VRAM read buffer. It is used in the NES to clear the screen when the console is reset either by the button or the [[CIC]], and in a dual-PPU system it can be used to [[wikipedia:Genlock|genlock]] the two PPUs together. | * /RST resets certain parts of the chip to their initial power-on state: the clock divider, video phase generator, scanline/pixel counters, and the even/odd frame toggle. It also keeps several registers zeroed out for a full frame: [[PPUCTRL]], [[PPUMASK]] ($2001), [[PPUSCROLL]] ($2005; the VRAM address latch "T", fine X scroll, and the H/V toggle), and the VRAM read buffer. It is used in the NES to clear the screen when the console is reset either by the button or the [[CIC]], and in a dual-PPU system it can be used to [[wikipedia:Genlock|genlock]] the two PPUs together. | ||
Revision as of 18:23, 5 August 2016
Pin out
.--\/--.
R/W -> |01 40| -- +5
D0 <> |02 39| -> ALE
D1 <> |03 38| <> PPU AD0
D2 <> |04 37| <> PPU AD1
D3 <> |05 36| <> PPU AD2
D4 <> |06 35| <> PPU AD3
D5 <> |07 34| <> PPU AD4
D6 <> |08 33| <> PPU AD5
D7 <> |09 32| <> PPU AD6
CPU A2 -> |10 31| <> PPU AD7
CPU A1 -> |11 30| -> PPU A8
CPU A0 -> |12 29| -> PPU A9
/CS -> |13 28| -> PPU A10
EXT0 <> |14 27| -> PPU A11
EXT1 <> |15 26| -> PPU A12
EXT2 <> |16 25| -> PPU A13
EXT3 <> |17 24| -> /RD
CLK -> |18 23| -> /WR
/INT <- |19 22| <- /RST
GND -- |20 21| -> VOUT
`------'
Signal description
- R/W, Dx, CPU A0, A1, A2 are signals from the CPU. CPU A2-A0 are tied to the corresponding CPU address pins and select the PPU register (0-7).
- /CS is generated by the 74139 (address decoder) on the mainboard to map the PPU regs in the CPU memory range from $2000 to $3FFF.
- EXTx allows the combination of two PPUs - setting the "slave" bit in the PPUCTRL ($2000) register causes the PPU to output palette indices to these pins, and clearing said bit causes it to instead read indices from these pins (and use them to select the background color). For the Vs. System and Playchoice PPUs, EXT0…2 are replaced with R, G, and B respectively. EXT3 is tied to ground; its functionality is unknown.
- CLK is the 21.47727 MHz (NTSC) or 26.6017 MHz (PAL) clock input. It is doubled for the color generator (and then divided by 12 to get the colorburst frequency) and also divided by 4 (NTSC) or 5 (PAL) for the pixel and memory clocks.
- /INT is connected to the CPU's /NMI pin.
- ALE (Address Latch Enable) goes high at the beginning of a PPU VRAM access and is used to latch the lower 8 bits of the PPU's address bus; see the PPU address bus section of PPU rendering. It stays high for one PPU cycle.
- PPU ADx (Address + Data) is the PPU's data bus, multiplexed with the lower 8 bits of the PPU's address bus.
- PPU A8-A13 are the top 6 bits of the PPU's address bus.
- /RD and /WR specify that the PPU is reading from or writing to VRAM. As an exception, writing to the internal palette range (3F00-3FFF) will not assert /WR.
- /RST resets certain parts of the chip to their initial power-on state: the clock divider, video phase generator, scanline/pixel counters, and the even/odd frame toggle. It also keeps several registers zeroed out for a full frame: PPUCTRL, PPUMASK ($2001), PPUSCROLL ($2005; the VRAM address latch "T", fine X scroll, and the H/V toggle), and the VRAM read buffer. It is used in the NES to clear the screen when the console is reset either by the button or the CIC, and in a dual-PPU system it can be used to genlock the two PPUs together.
- VOUT is the shifted analog video output. For the Vs. System and Playchoice PPUs, this is only the composite sync signal.
See also
- Wiring diagram of RF Famicom
- 電子機器(Electronics) Junker's redrawn schematic of the HVC-001
- Electronix Corp's redrawn schematic of the NES-001
- Note: Minor error on page "NES 3" for the power led / reset switch board: pin 5 connects to LED, pin 4 connects to switch, pin 3 is +5V.
