PPU

The NES PPU, or Picture Processing Unit, generates a composite video signal with 240 lines of pixels, designed to be received by a television. When the Famicom chipset was designed in the early 1980s, it was considered quite an advanced 2D picture generator for video games.

It has its own address space, which typically contains 10 kilobytes of memory: 8 kilobytes of ROM or RAM on the Game Pak (possibly more with one of the common mappers) to store the shapes of background and sprite tiles, plus 2 kilobytes of RAM in the console to store a map or two. Two separate, smaller address spaces hold a palette, which controls which colors are associated to various indices, and OAM (Object Attribute Memory), which stores the position, orientation, shape, and color of the sprites, or independent moving objects. These are internal to the PPU itself, and while the palette is made of static memory, OAM uses dynamic memory (which will slowly decay if the PPU is not rendering data).

Programmer's reference (printer friendly)

• Registers
• Pattern tables (tile graphics for background and sprites)
• Background graphics
  • Nametables
  • Attribute tables
• OAM (sprites)
• Palettes
• Memory map

Hardware behaviors

• Frame timing
• Power up state
• NMI
• Clock rate and other NTSC/PAL differences
• NTSC video
• The skinny on NES scrolling: What scroll and address writes do. (Very important for emulator authors. Also handy knowledge for developers implementing advanced screen splitting effects.)
• Rendering
• Sprite evaluation
• Sprite priority
• Overscan
• Visual 2C02: A hardware-level PPU simulator

Notes

• The NTSC video signal is made up of 262 scanlines, and 20 of those are spent in vblank state. After the program has received an NMI, it has about 2270 cycles to update the palette, sprites, and nametables as necessary before rendering begins.
• On NTSC systems, the PPU divides the master clock by 4 while the CPU uses the master clock divided by 12. Since both clocks are fed off the same master clock, this means that there are exactly three PPU ticks per CPU cycle, with no drifting over time (though the clock alignment might vary depending on when you press the Reset button).
• On PAL systems, the PPU divides the master clock by 5 while the CPU uses the master clock divided by 16. As a result, there are exactly 3.2 PPU ticks per CPU cycle.

See also

• 2C02 technical reference by Brad Taylor. (Pretty old at this point; information on the wiki might be more up-to-date.)