NES 2.0 submappers: Difference between revisions
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* Many games: [http://bootgod.dyndns.org:7777/search.php?keywords=serom&kwtype=pcb SEROM], [http://bootgod.dyndns.org:7777/search.php?keywords=SHROM&kwtype=pcb SHROM], [http://bootgod.dyndns.org:7777/search.php?keywords=SH1ROM&kwtype=pcb SH1ROM] | * Many games: [http://bootgod.dyndns.org:7777/search.php?keywords=serom&kwtype=pcb SEROM], [http://bootgod.dyndns.org:7777/search.php?keywords=SHROM&kwtype=pcb SHROM], [http://bootgod.dyndns.org:7777/search.php?keywords=SH1ROM&kwtype=pcb SH1ROM] | ||
Some of these games may be compatible with submapper 0 if $8000-BFFF is initialized to the low bank, and $C000-FFFF is initialized to the high bank, and the game never changes this. However, if an NES 2.0 header is specified, it should be presumed that a specific submapper is desired. | |||
== [[iNES Mapper 004|004]]: [[MMC3]] == | == [[iNES Mapper 004|004]]: [[MMC3]] == |
Revision as of 19:43, 7 August 2015
Submapper is a term used in the NES 2.0 header for 4-bit codes designating functionally distinct variants of iNES mappers that cannot be distinguished by the memory size fields alone. Most emulators using iNES format distinguish these using CRC, SHA-1, or other hashes of the PRG ROM and CHR ROM, but this works only for games published prior to 1997, not for fan translations or ROM hacks, and not for new games on the same mapper.
Submapper 0 represents the default iNES behavour, so that backward compatibility is maintained.
This document is a living specification. Proposals for new submappers should be made at: Proposals.
001: MMC1
Most MMC1 boards wire all PRG ROM address lines A14-A18 to the mapper's output in a fairly predictable manner.
Boards with CHR RAM wire PRG ROM A18 and the PRG RAM address lines to otherwise unused CHR bank outputs.
Boards designed to take a 32 KiB PRG ROM, either connect PRG ROM A14 to the MMC1's output (SIROM), or directly to CPU A14 (SEROM, SHROM, SH1ROM).
Submappers 1, 2 and 4 have register configurations that necessitate specific PRG ROM and PRG RAM sizes. These can alternatively be detected by the relevant size fields in the header.
001: 0
Normal behavior.
001: 1
SUROM reuses a CHR banking line as PRG RAM enable.
Can alternatively be identified by the following conditions:
- PRG ROM = 256k or 128k
- PRG RAM = 8k
- CHR RAM = 8k
- Dragon Warrior III
- Dragon Warrior IV / Dragon Quest IV
- Ninjara Hoi!
001: 2
SOROM reuses CHR banking lines as PRG RAM banking and enable.
Can alternatively be identified by the following conditions:
- PRG ROM = 256k or 128k
- PRG RAM = 16k
- CHR RAM = 8k
- Genghis Khan / Aoki Ookami to Shiroki Mejika: Genghis Khan
- Nobunaga's Ambition / Nobunaga no Yabou: Zenkokuban
- Romance of the Three Kingdoms
- Sangokushi
001: 3
Deprecated. Use iNES Mapper 155 instead.
001: 4
SXROM reuses CHR banking lines as PRG ROM banking and PRG RAM enable.
Can alternatively be identified by the following conditions:
- PRG ROM = 512k
- PRG RAM = 8k
- CHR RAM = 8k
- Final Fantasy I & II
- The Best Play Pro Yakyuu Special
- PR8. If extra RAM is missing, it gives a "DOES NOT WORK IN THIS EMULATOR" error.
001: 5
SEROM, SHROM, SH1ROM use a fixed 32k PRG ROM with no banking support. (This is distinct from SIROM which has 32k of bankable PRG ROM.)
PRG ROM A14 is connected directly to CPU A14 (and MMC1 A14 input) instead of MMC1 A14 output.
Some of these games may be compatible with submapper 0 if $8000-BFFF is initialized to the low bank, and $C000-FFFF is initialized to the high bank, and the game never changes this. However, if an NES 2.0 header is specified, it should be presumed that a specific submapper is desired.
004: MMC3
iNES Mapper 004 represents the most common boards using these four ICs: early MMC3, late MMC3, MC-ACC, and MMC6.
There are three known kinds of IRQ:
- MMC3A
- /IRQ is asserted on A12 rise, and loading the latch with 0 disables IRQ. Some chips labeled MMC3B also have this "old style" behavior. No games are known to rely on this behavior.
- MMC3C
- /IRQ is asserted on A12 rise, and loading the latch with 0 produces an IRQ on every scanline. Some chips labeled MMC3B also have this "new style" behavior, as does the MMC6. Some later games rely on this behavior.
- MC-ACC
- /IRQ is asserted on A12 fall, typically four pixels later than MMC3C. Interrupts can be produced every scanline, like the MMC3C.[1]
There are two known kinds of PRG RAM enable:
- MMC3
- One set of enable bits controls the entire chip.
- MMC6
- The first and second enables control the first and second half of PRG RAM, and an additional enable in bit 5 of $8000 controls the whole PRG RAM.
The TEROM and TFROM boards have two jumpers that can respectively disable IRQs and force hard-wired mirroring. It is believed that nothing was ever released that used them.
004: 0
Normal. (MMC3C)
004: 1
MMC6 has an alternative PRG-RAM enable and write protection scheme designed for its internal 1k PRG RAM.
- StarTropics
- StarTropics 2
004: 2
MMC3C with hard wired mirroring.
- TO DO: games that require this?
004: 3
MC-ACC
The MC-ACC is found on second-source PCBs manufactured by Acclaim found in 13 games from Alien 3 to WWF King of the Ring.
032: Irem G101
A variation of this mapper requires hardwired one-screen mirroring and entirely ignores writes to $9000.
032: 0
Normal (H/V mapper-controlled mirroring)
032: 1
CIRAM A10 is tied high (fixed one-screen mirroring) and PRG banking style is fixed as 8+8+16F
034: BNROM / NINA-001
This iNES mapper unfortunately combines the unrelated BNROM and NINA-001 mappers.
034: 0
Normal. Both mappers can be implemented simultaneously without incompatibility.
Because the NINA-001 supports CHR banking and BNROM does not, the presence of more than 8 KiB of CHR implies NINA-001, and could be used to select between two exclusive mapper implementations.
034: 1
NINA-001 only.
- (no extant games require this)
068: Sunsoft 4
In addition to its normal function, the Sunsoft 4 IC was used in Nantettatte!! Baseball which requires different PRG behavior:
068: 0
0: Normal (max 256KiB PRG)
068: 1
1: Sunsoft Dual Cartridge System a.k.a. NTB-ROM (max 128KiB PRG, licensing IC present, external option ROM of up to 128KiB should be selectable by a second menu)
- Nantettatte!! Baseball
071: Codemasters
Some games use this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. Others have hardwired horizontal or vertical mirroring.
Another variation of this mapper was used in the Quattro multicarts, but these have been reassigned to mapper 232.
071: 0
Hardwired horizontal or vertical mirroring.
071 : 1
Mapper controlled single-screen mirroring.
078: Cosmo Carrier / Holy Diver
This mapper unfortunately combines two games with incompatible mirroring control.
One game uses this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. The other can switch between horizontal and vertical mirroring, using a multiplexer between PPU A10 and PPU A11 whose output is sent to CIRAM A10.
078: 0
Unspecified.
078: 1
Single-screen mirroring (nibble-swapped mapper 152).
078: 2
Deprecated.
078: 3
Mapper-controlled H/V mirroring.
210: Namco 175 and 340
Mapper 210 doesn't distinguish between the 175's hardwired mirroring and 340's 1/H/V mirroring.
Also, previous confusion and compatibility code used by Namco when they were developing games means that many 175- and 340- using games are incorrectly tagged as mapper 19.
210: 0
No advisory statement is made (use runtime heuristics)
210: 1
Namco 175. Hardwired mirroring, no IRQ.
- See mapper 210 for a list of games.
210: 2
Namco 340. 1/H/V mirroring, no IRQ, no internal or external RAM.
- See mapper 210 for a list of games.
232: Quattro
Similar to #71 above, with a separate register controlling which 64 KiB outer bank of the PRG ROM is used. This is used for the Quattro multicarts.
The Aladdin Deck Enhancer version of these multicarts used a different banking scheme.
323: 0
0: Normal
232: 1
Aladdin Deck Enhancer variation. Swap the bits of the outer bank number.
- Quattro Adventure (Aladdin Deck Enhancer)
- Quattro Sports (Aladdin Deck Enhancer)