MMC4: Difference between revisions
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== Variants == | == Variants == | ||
Nintendo's [[MMC2]], used in [[PxROM]] boards, is a similar mapper with 8 KB switchable PRG ROM banks, a 24 KB fixed PRG ROM bank, no PRG RAM, and a slightly different behaviour in auto-switching on the left pattern table. | Nintendo's [[MMC2]], used in [[PxROM]] boards, is a similar mapper with 8 KB switchable PRG ROM banks, a 24 KB fixed PRG ROM bank, no PRG RAM, and a slightly different behaviour in auto-switching on the left pattern table. | ||
== See also == | |||
* [http://www.romhacking.net/documents/362/ NES Mapper List] by Dish | |||
* [http://nesdev.org/mmc4.txt Nintendo MMC4] (author unknown) |
Revision as of 09:41, 21 April 2015
The Nintendo MMC4 is an ASIC mapper, used on the FxROM board set. The iNES format assigns mapper 10 to these boards. The chip first appeared in August 1988.
Overview
- PRG ROM size: 256 KB
- PRG ROM bank size: 16 KB
- PRG RAM: 8 KB + battery
- CHR capacity: 128 KB
- CHR bank size: 4 KB
- Nametable mirroring: Vertical or horizontal, controlled by program
- Subject to bus conflicts: No
Banks
- CPU $6000-$7FFF: 8 KB fixed PRG RAM bank
- CPU $8000-$BFFF: 16 KB switchable PRG ROM bank
- CPU $C000-$FFFF: 16 KB PRG ROM bank, fixed to the last bank
- PPU $0000-$0FFF: Two 4 KB switchable CHR ROM banks
- PPU $1000-$1FFF: Two 4 KB switchable CHR ROM banks
When the PPU reads from specific tiles in the pattern table during rendering, the MMC4 sets a latch that tells it to use a different 4 KB bank number. On the background layer, this has the effect of setting a different bank for all tiles to the right of a given tile, virtually increasing the tile count limit from 256 to 512 without monopolising the CPU.
- PPU reads $0FD8 through $0FDF: latch 0 is set to $FD
- PPU reads $0FE8 through $0FEF: latch 0 is set to $FE
- PPU reads $1FD8 through $1FDF: latch 1 is set to $FD
- PPU reads $1FE8 through $1FEF: latch 1 is set to $FE
Registers
PRG ROM bank select ($A000-$AFFF)
7 bit 0 ---- ---- xxxx PPPP |||| ++++- Select 16 KB PRG ROM bank for CPU $8000-$BFFF
CHR ROM $FD/0000 bank select ($B000-$BFFF)
7 bit 0 ---- ---- xxxC CCCC | |||| +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF used when latch 0 = $FD
CHR ROM $FE/0000 bank select ($C000-$CFFF)
7 bit 0 ---- ---- xxxC CCCC | |||| +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF used when latch 0 = $FE
CHR ROM $FD/1000 bank select ($D000-$DFFF)
7 bit 0 ---- ---- xxxC CCCC | |||| +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF used when latch 1 = $FD
CHR ROM $FE/1000 bank select ($E000-$EFFF)
7 bit 0 ---- ---- xxxC CCCC | |||| +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF used when latch 1 = $FE
Mirroring ($F000-$FFFF)
7 bit 0 ---- ---- xxxx xxxM | +- Select nametable mirroring (0: vertical; 1: horizontal)
Hardware
The MMC4 is implemented in a 44-pin TQFP package. Only one revision is known to exist.
Variants
Nintendo's MMC2, used in PxROM boards, is a similar mapper with 8 KB switchable PRG ROM banks, a 24 KB fixed PRG ROM bank, no PRG RAM, and a slightly different behaviour in auto-switching on the left pattern table.
See also
- NES Mapper List by Dish
- Nintendo MMC4 (author unknown)