INES Mapper 176

Mapper 176 is used by FK23C- and FK23CA-based multicarts as well as the re-releases of Waixing games that were originally released on boards using a variety of mappers. Being primarily designed for multicarts, it consists of an MMC3 clone with extended PRG and CHR bankswitch registers. Its UNIF board names are BMC-FK23C, BMC-FK23CA and BMC-Super24in1SC03.

PRG and CHR bank switching is done via the normal MMC3 registers, whose high bits can be masked off if necessary, before being ORed with higher-order PRG and CHR Base bank bits. Additional Mode Register bits can be set to disable MMC3 PRG and/or CHR banking to solely use the PRG and CHR base directly as bank numbers in a GNROM-like fashion. A special CNROM mode allows ORing the CHR base with a data latch that responds to writes in the $8000-$FFFF range (except $A000-$BFFF). A few multicart menus use an extended MMC3 mode that provides full 1 KiB CHR bank granularity and switching the PRG banks that in a normal MMC3 are fixed. The RAM Configuration Register enables 32 KiB of WRAM, 16 KiB of which are non-volatile (i.e. battery-backed), and allows specifying that only the first 8 KiB of CHR memory are RAM.

Except for Variant 1, the power-on state is that all new registers are initialized to $00, causing the FK23C to mimic a standard MMC3, which means that the 8 KiB bank in CPU space at $E000 is the bank that ends the first 512 KiB ($7E000), even if the ROM image is larger than that. Several games and multicarts rely on the eight standard MMC3 bank registers being initialized to 0/2/4/5/6/7/0/1 and the four additional bank registers for Extended MMC3 Mode all being initialized to $FF in their power-on state.

Registers

FK23CA-variant boards have a DIP switch that changes the address mask at which the board hardware responds to CPU writes in the $5000-$5FFF range. The address mask is $10 SHL DIP, e.g. a DIP value of zero results in an address mask of $5010, a value of one in an address mask of $5020, and so on. Multicarts determine the DIP setting by attempting a PRG bankswitch at $5011, $5021, $5041, then checking after each attempt whether the bankswitch actually occured; subsequently registers are accessed at $5FFx, which will bankswitch at any DIP switch setting. A DIP setting of zero (address mask $5010) will produce a usable result for any ROM image, although the multicart's menu is sometimes found at other settings; such ROMs will not be recognizable as multicarts on emulators that do not allow changing the DIP switch setting and will instead appear to be oversized variants of one of the individual games.

Note that the registers in the $5000-$5FFF range can be temporarily disabled by the RAM Configuration Register ($A001). Waixing games do this apparently for protection purposes.

Mode Register ($5xx0)

7654 3210
---- ----
PCTm PMMM
|||| ||||
|||| |+++- PRG Mode/Mask (*1)
|||| |      0: MMC3 Bank AND $3F OR ((PRG Base SHL 1) AND NOT $3F)
|||| |      1: MMC3 Bank AND $1F OR ((PRG Base SHL 1) AND NOT $1F)
|||| |      2: MMC3 Bank AND $0F OR ((PRG Base SHL 1) AND NOT $0F)
|||| |      3: PRG Base selects the same 16 KiB PRG bank at CPU $8000 and $C000
|||| |      4: PRG Base SHR 1 selects 32 KiB PRG bank at CPU $8000
|||| |      5-7: Never used
|||| +---- PRG Base bit 7
|||+------ CHR Mask
|||         0: $FF in MMC3 CHR Mode (bit 6 clear), $03 in CNROM Mode ($5xx0 bit 6 set and $5xx3 bit 2/6 set)
|||         1: $FF/$FF/$7F (selected by bits 0-2) in MMC3 CHR Mode (bit 6 clear), $01 in CNROM Mode ($5xx0 bit 6 set and $5xx3 bit 2/6 set)
||+------- CHR Type (0: ROM, 1: RAM) (*2)
|+-------- CHR Mode
|           0: MMC3 Bank AND CHR Mask (bit 4) OR ((CHR Base SHL 3 AND NOT CHR Mask)
|           1: CHR Base selects 8 KiB CHR bank at PPU $8000. If CNROM Mode is active, the CNROM latch ANDed with the mask set by bit 4 and ORed with the CHR base.
+--------- PRG Base bit 8

• (*1) In Extended MMC3 Mode ($5xx3 bit 1 set), the MMC3 Bank mask is $7F regardless of the value of $5xx0 bits 0 to 2.
• (*2) The CHR Type (bit 5) is only meaningful on carts that have both CHR-RAM and CHR-ROM, such as the Rockman I-VI multicart. On carts that only have one type of CHR memory, this bit cannot be relied upon to correctly specify the installed memory type.

PRG Base Register ($5xx1)

7654 3210
---- ----
.PPP PPPP
 ||| ||||
 +++-++++- 16 KiB PRG Base bits 0-6

CHR Base Register ($5xx2)

7654 3210
---- ----
CPCC CCCC
|||| ||||
++++-++++- 8 KiB CHR Base bits 0-7
 |
 +-------- also: PRG Base bit 9

Writing to the CHR Base Register also resets the CNROM latch.

Extended Mode Register ($5xx3)

7654 3210
---- ----
.C.. .CE.
 |    || 
 |    |+- Extended MMC3 Mode (0: disable, 1: enable)
 +----+-- CNROM mode (0: disable, 1: enable)

Since all games that use CNROM mode always set both bits 2 and 6 simultaneously, it's not clear which one of these bits actually triggers the CNROM mode, and what the function of the other bit would be.

RAM Configuration Register ($A001)

This register functions like MMC3 register $A001 until bit 5 is set, which turns it into the RAM Configuration Register.

7654 3210
---- ----
RFE. ?CWW
|||  ||||
|||  ||++- Select 8 KiB PRG-RAM bank at $6000-$7FFF. Ignored if Bit 5 is clear.
|||  |+--- Select the memory type in the first 8 KiB of CHR space. Ignored if Bit 5 is clear.
|||  |      0: First 8 KiB are CHR-ROM
|||  |      1: First 8 KiB are CHR-RAM
|||  +---- Set to 1 by some Waixing games, meaning unknown
||+------- RAM Configuration Register Enable
||          0: RAM Configuration Register disabled, $A001 functions as on MMC3, 8 KiB of WRAM
||          1: RAM Configuration Register enabled, 32 KiB of WRAM
|+-------- FK23C Registers Enable. Ignored if Bit 5 is clear.
|           0: FK23C Registers disabled, $5000-$5FFF maps to the second 4 KiB of the 8 KiB WRAM bank 2
|           1: FK23C Registers enabled in the $5000-$5FFF range
+--------- PRG RAM enable (0: disable, 1: enable)

Of the four 8 KiB WRAM banks, only bank 1 and 3 are non-volatile. Games usually use bank 0 as work RAM, bank 2 for protection, and banks 1 and 3 for save game data.

The protection check involves disabling the FK23C registers in the $5000-$5FFF range by writing $Ax to $A001, then writing some code to $5000, $5010 and $5013 which will land in the second half of WRAM bank 2. After re-enabling the FK23C registers and copying save game data from banks 1 and/or 3 into work RAM in bank 0, bank 2 is switched in, and the three code code bytes originally written via the $5000-$5FFF window are copied to internal RAM and executed, which in many games are just a simple RTS. Most Waixing mapper 176 ROM images in GoodNES 3.23b have been hacked to partially remove this protection and to allow them to be run in emulators that merely ignore the WRAM writes to $5000, $5010 and $5013.

CNROM latch ($8000-$9FFF, $C000-$FFFF)

If CNROM Mode is active ($5xx0 bit 6 set and $5xx3 bit 2/6 set), writes to these ranges will update a data latch similar to a normal CNROM board, with the latch value being masked according to $5xx0 bit 4 before being ORed with the CHR Base.

MMC3-compatible registers ($8000/$8001, $A000, $C000/$C001, $E000/$E001)

If the "Extended MMC3 Mode" bit in register $5xx3 is clear, then these registers function identically to the MMC3. If the "Extended MMC3 Mode" bit is set, four more bank registers become available at $8000/$8001, so that the original two 2 KiB CHR banks become four 1 KiB CHR banks, and the two fixed 8 KiB PRG banks become selectable:

Register $8000 if $5xx3 bit 1 is set (Mask: $E001):
7  bit  0
---- ----
CP.. RRRR
||   ||||
||   ++++- Specify which bank register to update on next write to Bank Data register
||         0: Select 1 KB CHR bank at PPU $0000-$03FF (or $1000-$13FF)
||         1: Select 1 KB CHR bank at PPU $0800-$0BFF (or $1800-$1BFF)
||         2: Select 1 KB CHR bank at PPU $1000-$13FF (or $0000-$03FF)
||         3: Select 1 KB CHR bank at PPU $1400-$17FF (or $0400-$07FF)
||         4: Select 1 KB CHR bank at PPU $1800-$1BFF (or $0800-$0BFF)
||         5: Select 1 KB CHR bank at PPU $1C00-$1FFF (or $0C00-$0FFF)
||         6: Select 8 KB PRG ROM bank at $8000-$9FFF (or $C000-$DFFF)
||         7: Select 8 KB PRG ROM bank at $A000-$BFFF
||         8: Select 8 KB PRG ROM bank at $C000-$DFFF (or $8000-$9FFF)
||         9: Select 8 KB PRG ROM bank at $E000-$FFFF
||         A: Select 1 KB CHR bank at PPU $0400-$07FF (or $1400-$17FF)
||         B: Select 1 KB CHR bank at PPU $0C00-$0FFF (or $1C00-$1FFF)
|+-------- PRG A14 inversion
+--------- CHR A12 inversion

If the "Extended MMC3 Mode" bit is set, a second Mirroring bit in register $A000 becomes available, allowing single-screen mirroring to be selected in addition to Vertical and Horizontal Mirroring:

Register $A000 if $5xx3 bit 1 is set (Mask: $E001):
7  bit  0
---- ----
.... ..MM
       ++- Select nametable mirroring 
           0: Vertical
           1: Horizontal
           2: Single-screen, page 0
           3: Single-screen, page 1

Variants

No submappers have been assigned yet for incompatible variants of the hardware.

0: Normal

Powers up with the PRG Base Register set to $00, causing the FK23C to mimic a standard MMC3, which means that the 8 KiB bank in CPU space at $E000 is the bank that ends the first 512 KiB ($7E000), even if the ROM image is larger than that.

1: Extra PRG for multicart menu

A few multicarts hold four 128 KiB PRG-ROM-bearing games with no space left in those 512 KiB for the multicart menu. The menu is then put into a separate 32 KiB PRG bank that is mapped into the full PRG address space as the end of a second 512 KiB PRG-ROM bank, the other 480 KiB of that second 512 KiB PRG-ROM bank being empty. Carts in that configuration thus boot up with the 8 KiB bank in CPU space at $E000 being the bank that ends the second 512 KiB ($FE000), by initializing the PRG Base Register to $60 (or $20). These carts can be automatically detected by the fact that they, and only they, all have 1024 KiB of PRG-ROM and 1024 KiB of CHR-ROM.

2: Flipped MMC3 Registers $46 and $47

For unknown reasons, the two very large (16 MiB of PRG-ROM) multicarts swap MMC3 registers $46 and $47, but not $06 and $07. Individual MMC3 games, such as Kage, on these multicarts were modified to account for this. These carts can be automatically detected by the fact that they contain 16384 KiB of PRG-ROM.

Notes

• The RAM Configuration Register is not just enabled by Waixing games, but also by some of the later FK23C multicarts, which does not imply however that they are actually equipped with PRG-RAM.
• If a cart has both CHR-ROM and CHR-RAM, then a NES 2.0 header must be used to specify that, as most emulators disable CHR-RAM completely if a NES 1.0 header with CHR-ROM is found.
• Large multicarts with no CHR-ROM use large amounts of CHR-RAM into which an individual game's CHR data is copied when it is selected. CHR-RAM sizes range from 128 KiB (10-in-1 Omake Game, 150-in-1 Real Game, 245-in-1 Real Game) and even 256 KiB (120-in-1 Waixing Games).
• Many Waixing games in GoodNES 3.23b that correctly should be set to mapper 176 are incorrectly set to Mapper 30. These games were converted from Waixing's proprietary (and encrypted) .WXN format; the Mapper 30 designation is the result of interpreting these .WXN files' non-iNES header as if it were an iNES header.
• The ROM that GoodNES 3.23b calls "Mortal Kombat Trilogy - 8 People (M1274) (Ch) [!].zip" is commonly set to Mapper 176 even though it does not use FK23C-compatible register addresses and content. Despite what GoodNES 3.23b calls it, it is actually an earlier version of "KY-9005 9-in-1" multicart, which has a later version that does use FK23C hardware.
• The WXN version of 帝国风暴 (Dìguó Fēngbào) - Napoleon's War requires PAL or Dendy timing. On NTSC systems, the game will freeze before the main game screen is shown because of an excessively long NMI handler. The game will appear to run even in NTSC mode on some emulators that do not emulate the RAM Configuration Register and instead interpret the $E0 write to $A001 as an MMC3 to mean "deny any writes to WRAM". The game map will be empty in those emulators however, rendering the game unplayable.
• The game Five Kids on the 120-in-1 Waixing multicart is glitched because it writes to OneBus bank registers in its IRQ handler.
• FCEUX emulates INES Mapper 199 as a duplicate of Mapper 176 behaving as if bit 2 of the RAM Configuration Register were permanently set and as if Extended MMC3 Mode were permanently active, probably because the function of those bits was not known for a long time.