APU Noise: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
m (Created page with 'The NES APU triangle channel generates a pseudo-triangle wave. It has no volume control; the waveform is either cycling or suspended. It includes a ''linear counter'', an...')
 
m (The triangle section was copied inside the noise one by accident.)
Line 1: Line 1:
The [[APU|NES APU]] triangle channel generates a pseudo-triangle wave. It has no volume control; the waveform is either cycling or suspended. It includes a ''linear counter'', an extra duration timer of higher accuracy than the [[APU Length Counter|length counter]].
The [[NES APU]] noise channel generates pseudo-random 1-bit noise at 16 different frequencies.
 
The noise channel contains the following: [[APU Envelope|envelope generator]], [[APU Misc|timer]], shift register with feedback, [[APU Length Counter|length counter]].


The triangle channel contains the following: [[APU Misc|timer]], linear counter, [[APU Length Counter|length counter]], halt flag, [[APU Misc|sequencer]]. The linear counter contains an internal halt flag and counter.
<pre>
<pre>
      Linear Counter   Length Counter
  Timer --> Shift Register   Length Counter
            |                |
                  |                |
            v                v
                  v                v
Timer ---> Gate ----------> Gate ---> Sequencer ---> (to mixer)
Envelope -------> Gate ----------> Gate --> (to mixer)
</pre>
</pre>


{| border=1
{| border=1
| '''$4008''' || <tt>CRRR.RRRR</tt> || '''Linear counter''' setup (write)
| '''$400C''' || <tt>--le.eeee</tt> || '''[[APU Length Counter|Length counter halt]]''' and '''[[APU Envelope|envelope]]''' (write)
|-
|-
| bit 7 || <tt>C---.----</tt> || Control flag (this bit is also the [[APU Length Counter|length counter halt flag]])
|colspan=3| &nbsp;
|-
| bits 6-0 || <tt>-RRR RRRR</tt> || Counter reload value
|-
|-
|colspan=3| &nbsp;
| '''$400E''' || <tt>L---.PPPP</tt> || '''Loop and period''' (write)
|-
|-
| '''$400A''' || <tt>LLLL.LLLL</tt> || '''[[APU Misc|Timer low]]''' (write)
| bit 7 || <tt>L--- ----</tt> || Loop flag
|-
|-
| bits 7-0 || <tt>LLLL LLLL</tt> || Timer low 8 bits
| bits 3-0 || <tt>---- PPPP</tt> || The timer period is set to entry P of the following:<br>
<!-- If you modify this table, keep the values comma-separated so they can be used without changes in a program -->
<pre>
Rate  $0 $1  $2  $3  $4  $5  $6  $7  $8   $9  $A  $B  $C    $D    $E    $F
      --------------------------------------------------------------------------
NTSC  4, 8, 16, 32, 64, 96, 128, 160, 202, 254, 380, 508, 762, 1016, 2034, 4068
PAL    4, 7, 14, 30, 60, 88, 118, 148, 188, 236, 354, 472, 708,  944, 1890, 3778
</pre>
|-
|-
|colspan=3| &nbsp;
|colspan=3| &nbsp;
|-
|-
| '''$400B''' || <tt>llll.lHHH</tt> || '''[[APU Length Counter|Length counter load]]''' and '''[[APU Misc|timer high]]''' (write)
| '''$400F''' || <tt>llll.l---</tt> || '''[[APU Length Counter|Length counter load]]''' and '''[[APU Envelope|envelope restart]]''' (write)
|-
| bits 2-0 || <tt>---- -HHH</tt> || Timer high 3 bits
|-
|colspan=2| Side effects || Sets the halt flag
|}
|}


The [[APU Misc|timer's period]] is the 11-bit value (<tt>%HHH.LLLLLLLL</tt>) formed by timer high and timer low, ''plus one''.
When the timer clocks the shift register, the following two actions occur in order:
 
# Bit 15 of the shift register is replaced with the exclusive-OR of bit 0 and one other bit: bit 6 if loop is set, otherwise bit 1.<br>Shift register bits: <tt>%F-------.-6----10</tt>
# The shift register is shifted one bit right (bit 0 is lost).


When the [[APU Frame Counter|frame counter]] generates a linear counter clock, the following actions occur in order:
This results in a pseudo-random bit sequence, 32767 bits long when loop is clear, otherwise 93 bits long (the particular 93-bit sequence depends on where in the 32767-bit sequence the shift register was when loop was set).
# If the halt flag is set, the linear counter is reloaded with the counter reload value, otherwise if the linear counter is non-zero, it is decremented.
# If the control flag is clear, the halt flag is cleared.


The sequencer is clocked by the timer except when
The [[APU Mixer|mixer]] receives the current [[APU Envelope|envelope volume]] except when
* The linear counter is zero, or
* Bit 0 of the shift register is set, or
* The [[APU Length Counter|length counter]] is zero
* The [[APU Length Counter|length counter]] is zero


The sequencer sends the following looping 32-step sequence of values to the [[APU Mixer|mixer]]:
On power-up, the shift register is loaded with the value 1.
<pre>
15, 14, 13, 12, 11, 10,  9,  8,  7,  6,  5,  4,  3,  2,  1,  0
0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15
</pre>
 
At the lowest two [[APU Misc|timer]] periods ($400B = 0 and $400A = 0 or 1), the resulting frequency is so high that the [[APU Mixer|mixer]] effectively receives a value half way between 7 and 8.

Revision as of 05:28, 1 July 2009

The NES APU noise channel generates pseudo-random 1-bit noise at 16 different frequencies.

The noise channel contains the following: envelope generator, timer, shift register with feedback, length counter. 

   Timer --> Shift Register   Length Counter
                   |                |
                   v                v
Envelope -------> Gate ----------> Gate --> (to mixer)
$400C --le.eeee Length counter halt and envelope (write)
 
$400E L---.PPPP Loop and period (write)
bit 7 L--- ---- Loop flag
bits 3-0 ---- PPPP The timer period is set to entry P of the following:
Rate  $0 $1  $2  $3  $4  $5   $6   $7   $8   $9   $A   $B   $C    $D    $E    $F
      --------------------------------------------------------------------------
NTSC   4, 8, 16, 32, 64, 96, 128, 160, 202, 254, 380, 508, 762, 1016, 2034, 4068
PAL    4, 7, 14, 30, 60, 88, 118, 148, 188, 236, 354, 472, 708,  944, 1890, 3778
 
$400F llll.l--- Length counter load and envelope restart (write)

When the timer clocks the shift register, the following two actions occur in order:

  1. Bit 15 of the shift register is replaced with the exclusive-OR of bit 0 and one other bit: bit 6 if loop is set, otherwise bit 1.
    Shift register bits: %F-------.-6----10
  2. The shift register is shifted one bit right (bit 0 is lost).

This results in a pseudo-random bit sequence, 32767 bits long when loop is clear, otherwise 93 bits long (the particular 93-bit sequence depends on where in the 32767-bit sequence the shift register was when loop was set).

The mixer receives the current envelope volume except when

On power-up, the shift register is loaded with the value 1.

Retrieved from "https://www.nesdev.org/w/index.php?title=APU_Noise&oldid=501"