Family Computer Network Adapter: Difference between revisions

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(Creates Network Adapter page with initial findings from software.)
 
(Fixes controller bit information based on additional research.)
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# Repeat from step 3 until 24-bit report is read.
# Repeat from step 3 until 24-bit report is read.


The controller report is sent in order. Bits 0-7 match a [[standard controller]]. If any of bits 8, 9, 16, or 17 are 1, the read is rejected. Because the 15 additional buttons should only leave 1 reserved bit, it is not understood why 4 bits are expected to be 0.
The controller report is sent in order. Bits 0-7 match a [[standard controller]]. It is not yet known if the remaining bits match the [[Famicom Network Controller]]. Available software nullifies the input if 2 or more buttons are pressed, but allows any combination of bits 8, 9, 16, and 17 if no other button is pressed.


===Packets===
===Packets===

Revision as of 20:28, 15 March 2022

The Family Computer Network Adapter (HVC-035) is an unreleased Famicom modem used with the Family Computer Disk System via the RAM adapter's expansion port. A controller similar to the Famicom Network Controller attaches directly to the adapter, and like the later-released Famicom Network System, the adapter provides kanji graphics for use by software. A speaker is also believed to be built in to the unit.

Interface

The adapter uses the FDS expansion port, which is mapped to the low 7 bits of $4026 for writes and $4033 for reads. These bits are bidirectional and each side can pull them low. As such, to be able to receive data on a bit, the console must have first set that bit.

6 bit  0
--- ----
PDC ARWK
||| ||||
||| |||+- Kanji/controller data
||| ||+-- Kanji index write clock, and
||| ||    Kanji/controller read selector (0 = kanji, 1 = controller)
||| |+--- Kanji/controller read clock
||| +---- Adapter ready for packet transfer (0 = ready), and
|||       Adapter packet transfer clock
||+------ Console ready for packet transfer (0 = ready), and
||        Console packet transfer clock
|+------- Packet data
+-------- Packet available (0 = available)

Note below that all bits modified in the same step should be written in a single write.

Kanji graphics

The adapter provides 4096 16x16 1-bit-per-pixel characters, presumed to be mostly kanji. The console writes a 12-bit index to the adapter and then reads the corresponding 32-byte character back.

To write the kanji index:

  1. Set bit 2 and clear bit 1.
  2. Write index bit (low bit first) to bit 0.
  3. Set bit 1.
  4. Clear bit 1.
  5. Repeat from step 2 until 12-bit index is written.

To read the kanji data:

  1. (Bit 2 should be set and bit 1 should be clear from writing the index.)
  2. Set bit 0.
  3. Clear bit 2.
  4. Read data bit (low bit first) from bit 0.
  5. Set bit 2.
  6. Repeat from step 3 until 32-byte data is read.

Controller

The adapter uses a 23-button controller that extends the standard controller with a 15-button keypad. This controller connects directly to the adapter.

To read the controller:

  1. Set bit 2, clear bit 1, and set bit 0.
  2. Set bit 1.
  3. Clear bit 2.
  4. Read data bit from bit 0.
  5. Set bit 2.
  6. Repeat from step 3 until 24-bit report is read.

The controller report is sent in order. Bits 0-7 match a standard controller. It is not yet known if the remaining bits match the Famicom Network Controller. Available software nullifies the input if 2 or more buttons are pressed, but allows any combination of bits 8, 9, 16, and 17 if no other button is pressed.

Packets

A bidirectional interface is used to transfer packets between the console and adapter. These packets are terminated when byte value $1F is seen. The console software transfers in batches of up to 20 bytes at a time and picks up where it left off the next frame, as necessary. The format and functionality of these packets is not understood.

Send

To send a packet to the adapter:

  1. Verify bit 6 and bit 3 are set. If not, receive the pending packet, instead.
  2. Clear bit 4.
  3. Verify bit 6 and bit 3 are set. If not, set bit 4 and receive the pending packet, instead.
  4. Clear bit 6.
  5. Wait for bit 3 to toggle.
    • If toggle does not occur soon enough, fail.
  6. Toggle bit 4 and write data bit (low bit first) to bit 5.
  7. Repeat from step 5 until the last byte sent had value $1F.
  8. Wait for bit 3 to become clear.
    • If clear does not occur soon enough, fail.
  9. Set bit 6, set bit 5, and set bit 4.
  10. Wait for bit 3 to become set.
    • If set does not occur soon enough, fail.

If the send fails:

  1. Set bit 6, set bit 5, and set bit 4.

Receive

If bit 6 and bit 4 are both 0, the adapter is ready to send a packet. To receive a packet from the adapter:

  1. Clear bit 4.
  2. Wait for bit 3 to toggle.
    • If bit 6 becomes set while waiting, fail.
    • If toggle does not occur soon enough, fail.
  3. Read data bit (low bit first) from bit 5.
  4. Toggle bit 4.
  5. Repeat from step 2 until the last byte received had value $1F.
  6. Wait for bit 6 and bit 3 to be set.
    • If both bits do not set soon enough, fail.
  7. Set bit 4.

If the receive fails:

  1. Set bit 4.