User:Ulfalizer: Difference between revisions
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(Read/writes seem to happen during φ2) |
(Add quick link to clocks section of tutorial) |
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* Values appear to be read during '''φ2''' ('''db''x''''' pins buffered on '''cclk'''). | * Values appear to be read during '''φ2''' ('''db''x''''' pins buffered on '''cclk'''). | ||
* '''db''' changes during '''φ2''' for writes too. | * '''db''' changes during '''φ2''' for writes too. | ||
* [[Visual_circuit_tutorial#Clocks|Clocks section of tutorial]]. | |||
== M2 duty cycle == | == M2 duty cycle == | ||
Revision as of 19:25, 5 June 2013
Misc. timing stuff brought together in one place
Read (LDA $1234, NOP)
Tick-by-tick from http://nesdev.org/6502_cpu.txt interleaved with steps from Visual 2A03:
# address R/W description
--- ------- --- -------------------------------------------------
1 PC R fetch opcode, increment PC
ab db rw pc phi2
0000 ad 1 0000 0
0000 ad 1 0000 1
2 PC R fetch low byte of address, increment PC
ab db rw pc phi2
0001 34 1 0001 0
0001 34 1 0001 1
3 PC R fetch high byte of address, increment PC
ab db rw pc phi2
0002 12 1 0002 0
0002 12 1 0002 1
4 address R read from effective address
ab db rw pc phi2
1234 00 1 0003 0
1234 00 1 0003 1
Write (LDA #$AB, STA $1234, NOP)
Tick-by-tick from http://nesdev.org/6502_cpu.txt interleaved with steps from Visual 2A03:
# address R/W description
--- ------- --- ------------------------------------------
1 PC R fetch opcode, increment PC
ab db rw pc phi2
0002 8d 1 0002 0
0002 8d 1 0002 1
2 PC R fetch low byte of address, increment PC
ab db rw pc phi2
0003 34 1 0003 0
0003 34 1 0003 1
3 PC R fetch high byte of address, increment PC
ab db rw pc phi2
0004 12 1 0004 0
0004 12 1 0004 1
4 address W write register to effective address
ab db rw pc phi2
1234 12 0 0005 0
1234 ab 0 0005 1
Read/write observations
- Values appear to be read during φ2 (dbx pins buffered on cclk).
- db changes during φ2 for writes too.
- Clocks section of tutorial.
M2 duty cycle
The M2 duty cycle is 5/8 - forum post and CPU pin-out page. Low for 9/8 PPU cycles, high for 15/8 PPU cycles. Low for 4.5 master cycles, high for 7.5 master cycles.
