Talk:RAMBO-1: Difference between revisions

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(→‎Alternate IRQ timing: Figured out the IRQ timing!)
m (→‎Alternate IRQ timing: Minor fixes.)
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'''When the IRQ is clocked by CPU or scanline modes:'''
'''When the IRQ is clocked by CPU or scanline modes:'''
*If the IRQ counter++ == IRQ latch:
*IF IRQ_counter++ == IRQ_latch:
**If IRQ_enabled == true, wait 4 CPU cycles then trigger an IRQ AND clear IRQ_counter.
**IF IRQ_enable == true, wait 4 CPU cycles, then trigger an IRQ '''AND''' clear IRQ_counter.
*ELSE if the IRQ_clear == '''true''':
*ELSE IF IRQ_clear == '''true''':
**''IRQ counter'' is set to zero.
**Clear IRQ_counter and IRQ_clear = '''false'''.
**''IRQ clear flag'' is set to '''false'''.
 
--[[User:Zepper|Zepper]] ([[User talk:Zepper|talk]]) 16:22, 7 July 2017 (MDT)

Revision as of 01:55, 8 July 2017

As for the 2mb PRG, I'm not sure if the cart actually supports that much ROM, but the PRG registers apparently are 8 bits, and 8kb * $100 = 2048kb = 2mb. --Drag 03:05, 9 November 2011 (UTC)

IRQ related - Hard Drivin'

Suggested changes for the Mapper64 IRQ. It makes Hard Drivin' to work fine. No other games are affected with this change. Every cycle on 6502 is either a read or a write cycle. So, you update the IRQ counter in the next CPU cycle:

  • IF $C001 was written to after previous clock
    • reload IRQ counter with IRQ Reload value PLUS ONE
  • ELSE IF IRQ counter is 0
    • reload IRQ counter with IRQ Reload value

When the IRQ is clocked by the mapper (in scanline or cycle mode):

    • Decrement IRQ counter by 1
    • IF IRQ counter is now 0 AND IRQs are enabled
      • wait one M2 cycle, then trigger IRQ

Hard Drivin' works. --Zepper (talk) 17:57, 14 January 2014 (MST)

Alternate IRQ timing

This is how to get 3 games working: Klax, Skull&Crossbones and Hard Drivin'.

  • Address mask: $E001.
  • Register $C000: IRQ_latch = value AND $FE (last bit is NOT used), IRQ_clear = true.
  • Register $C001: IRQ_mode = value AND $01, IRQ_clear = true.
  • Register $E000: IRQ_enable = false, acknowledges IRQ.
  • Register $E001: IRQ_enable = true, acknowledges IRQ.


When the IRQ is clocked by CPU or scanline modes:

  • IF IRQ_counter++ == IRQ_latch:
    • IF IRQ_enable == true, wait 4 CPU cycles, then trigger an IRQ AND clear IRQ_counter.
  • ELSE IF IRQ_clear == true:
    • Clear IRQ_counter and IRQ_clear = false.