CPU power up state: Difference between revisions
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:APU mode in $4017 was unchanged | :APU mode in $4017 was unchanged | ||
:APU was silenced ($4015 = 0) | :APU was silenced ($4015 = 0) | ||
:APU triangle phase is reset to 0 | :APU triangle phase is reset to 0 (i.e. outputs a value of 15, the first step of its waveform) | ||
== See also == | == See also == | ||
*[[PPU power up state]] | *[[PPU power up state]] | ||
== Notes == | == Notes == | ||
Revision as of 08:20, 21 July 2019
The following results are from a US (NTSC) NES, original front-loading design, RP2A03G CPU chip, NES-CPU-07 main board revision, manufactured in 1988. The memory values are probably slightly different for each individual NES console. Please note that you should NOT rely on the state of any registers after Power-UP and especially not the stack register and RAM ($0000-$07FF).
At power-up
- P = $34[1] (IRQ disabled)[2]
- A, X, Y = 0
- S = $FD[3]
- $4017 = $00 (frame irq enabled)
- $4015 = $00 (all channels disabled)
- $4000-$400F = $00 (not sure about $4010-$4013)
- All 15 bits of noise channel LFSR = $0000[4]. The first time the LFSR is clocked from the all-0s state, it will shift in a 1.
- Internal memory ($0000-$07FF) has unreliable startup state. Some machines may have consistent RAM contents at power-on, but others do not.
- Emulators often implement a consistent RAM startup state (e.g. all $00 or $FF, or a particular pattern), and flash carts like the PowerPak may partially or fully initialize RAM before starting a program, so an NES programmer must be careful not to rely on the startup contents of RAM.
After reset
- A, X, Y were not affected
- S was decremented by 3 (but nothing was written to the stack)[3]
- The I (IRQ disable) flag was set to true (status ORed with $04)
- The internal memory was unchanged
- APU mode in $4017 was unchanged
- APU was silenced ($4015 = 0)
- APU triangle phase is reset to 0 (i.e. outputs a value of 15, the first step of its waveform)
See also
Notes
- ↑ The golden log of nestest differs from this in the irrelevant bits 5 and 4 of P
- ↑ IRQ was first asserted about 1/60 second after power-up, by APU.
- ↑ 3.0 3.1 RESET uses the logic shared with NMI, IRQ, and BRK that would push PC and P. However, like some but not all 6502s, the 2A03 prohibits writes during reset. This test relies on open bus being precharged by these reads. See 27c3: Reverse Engineering the MOS 6502 CPU (en) from 41:45 onward for details
- ↑ Noise channel init log
