Talk:APU DMC: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(Created page with 'Similarly to the noise channel, the DPCM channel's frequency counter [http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/ on the die] is a '''9-bit linear …')
 
m (this too)
Line 1: Line 1:
Similarly to the [[APU Noise|noise channel]], the DPCM channel's frequency counter [http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/ on the die] is a '''9-bit linear feedback shift register''' (with taps at the 5th and 9th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '100000000', the cycle counts (for NTSC) match exactly. --[[User:Quietust|Quietust]] 05:00, 23 January 2011 (UTC)
Similarly to the [[APU Noise|noise channel]], the DPCM channel's frequency counter [http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/ on the die] is a '''9-bit linear feedback shift register''' (with taps at the 5th and 9th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '100000000', the cycle counts (for NTSC) match once multiplied by 2. --[[User:Quietust|Quietust]] 05:00, 23 January 2011 (UTC)

Revision as of 00:29, 24 January 2011

Similarly to the noise channel, the DPCM channel's frequency counter on the die is a 9-bit linear feedback shift register (with taps at the 5th and 9th bits); when I take the counter values from the on-die ROM and run the LFSR until the result is '100000000', the cycle counts (for NTSC) match once multiplied by 2. --Quietust 05:00, 23 January 2011 (UTC)